EPM5032DI-25 vs EPM5032DM 比較
詳細並排比較 EPM5032DI-25 由 Altera 與 EPM5032DM 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032DI-25 | EPM5032DM |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 5000 | — |
| Device Type | UV-erasable Programmable Logic Device (PLD) | — |
| Architecture | PAL-type, CMOS, AND-OR sum-of-products | — |
| Macrocells | 32 | 32 |
| Product Terms | 320 | — |
| Logic Gates | [DATA_NEEDED: equivalent gate count] | — |
| Dedicated Inputs | 7 | — |
| Bidirectional I/O Pins | 16 | — |
| Total Array Inputs | 24 | — |
| Registered Outputs | 16 | — |
| Global Clocks | 1 | — |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| 供應電壓 | 5 V | — |
| Process Technology | CMOS | CMOS EEPROM |
| 封裝 | Ceramic DIP, windowed (UV-erasable) | CDIP-28 (ceramic windowed DIP, 28-pin) |
| 腳位數 | [DATA_NEEDED: exact pin count - 24 or 28] | — |
| 工作溫度 | 0C to +70C (commercial) | -55C to +125C (military/extended, ceramic package) |
| I/O Standard | TTL-compatible | — |
| Programmability | UV-erasable, EPROM-based | — |
| Development Tool | MAX+PLUS II / A+PLUS | — |
| RoHS 狀態 | [DATA_NEEDED: likely non-compliant due to ceramic DIP] | Non-compliant (ceramic DIP with UV window) |
| Lifecycle | Not Recommended for New Designs (NRND) | — |
| Device Family | — | MAX 5000 |
| Usable Gates | — | 600 to 1000 (typical) |
| Logic Inputs | — | 32 |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Standby Current | — | [DATA_NEEDED: ICC standby current] |
| Programming Technology | — | UV-erasable (windowed) EEPROM |
| Logic Function | — | Combinational and registered (synchronous) |
| Output Polarity | — | Programmable |
| Program Retention | — | Non-volatile (EEPROM) |
| 安裝類型 | — | Through-hole (DIP) |
| Lead-Free | — | No (ceramic DIP contains lead) |