EPM5032DI25 vs EPM5032DC-15 比較
詳細並排比較 EPM5032DI25 由 Altera 與 EPM5032DC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM5032DC-15 - 600-Gate, 32-Macrocell UV PLD | Altera MAX 5000 | DIP-28
EPM5032DC-15 Obsolete規格比較
| 參數 | EPM5032DI25 | EPM5032DC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-erasable EPLD (CMOS EPROM-based) | UV-erasable EPLD (PAL-type CMOS) |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 2 | — |
| Product Terms | 320 | — |
| Output Macrocells | 16 | — |
| Bidirectional I/O Pins | 16 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs | 24 | — |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V (nominal) |
| I/O Standard | TTL-compatible | — |
| 封裝 | 24-pin Ceramic DIP (DI) with quartz window | CERDIP-28 (windowed, through-hole) |
| Programming Technology | UV-EPROM (erasable via quartz window) | — |
| Usable Gates | — | 600 |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Toggle Frequency (fMAX) | — | 83.3 MHz |
| Logic Family | — | CMOS, TTL-compatible I/O |
| Programmable Pins | — | 16 bidirectional I/O + 4 dedicated input = 20 |
| Total Package Pins | — | 28 |
| 安裝類型 | — | Through-Hole (DIP) |
| 工作溫度 | — | 0C to +70C (commercial) |
| Erasure Method | — | UV light through ceramic quartz window |
| Process Technology | — | CMOS |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status] |
| Lead-Free | — | unknown |