EPM5032JC vs EPM5032DC 比較
詳細並排比較 EPM5032JC 由 Altera 與 EPM5032DC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032JC | EPM5032DC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 EPLD | MAX 5000 |
| Macrocells | 32 | 32 |
| Logic Gates | 600 usable gates | — |
| Maximum I/O Pins | 40 | — |
| Propagation Delay (tPD) | [DATA_NEEDED: specific speed grade value] | — |
| Supply Voltage (VCC) | 5 V | — |
| Input Type | TTL-compatible | — |
| 輸出類型 | TTL/CMOS-compatible | — |
| 封裝 | PLCC-44 | DIP-24 (ceramic, windowed) |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C |
| 安裝類型 | Surface Mount (J-lead) | Through-hole (DIP) |
| Programmability | UV-erasable (windowed ceramic) / OTP variants | — |
| Design Software | MAX+PLUS II / Quartus legacy | — |
| JEDEC Standard | JEDEC PLCC-44 footprint | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS status] |
| Lead-Free | unknown | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 1 |
| Speed Grade | — | DC (commercial) |
| Technology | — | Bipolar EPROM, UV-erasable |
| Programmable Logic Elements | — | AND array + fixed OR array per macrocell |
| Configuration Memory | — | EPROM (UV-erasable via package window) |
| 腳位數 | — | 24 |
| Programming Tool | — | Altera MAX+PLUS II / A+PLUS legacy |
| 生命週期狀態 | — | Obsolete (mature legacy) |