EPM5032LC-15 vs EPM5032JC-20 比較
詳細並排比較 EPM5032LC-15 由 Altera 與 EPM5032JC-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032LC-15 | EPM5032JC-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 EPLD | MAX 5000 |
| Architecture | PAL-type AND/OR with PIA | PAL-type AND-OR array with PIA interconnect |
| Usable Gates | 600 | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 4 | 1 |
| Dedicated Inputs | 7 | 8 |
| Bidirectional I/O Pins | 16 | — |
| Maximum Operating Frequency | 83.3 MHz | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS EPROM, 1.0 um process | — |
| Programmability | UV-Erasable / OTP | — |
| 封裝 | JLCC-28 (windowed ceramic) | 68-pin JLCC (windowed ceramic) |
| 工作溫度 | 0C to +70C (commercial) | — |
| RoHS 狀態 | Non-compliant (contains Pb, ceramic-windowed package) | — |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Product Terms (P-terms) | — | 320 |
| Propagation Delay (tPD) | — | 20 ns |
| 最大時脈頻率 | — | 62.5 MHz |
| Setup Time | — | 10 ns |
| I/O Lines | — | 16 (bidirectional) |
| Total Inputs | — | 24 |
| Process Technology | — | CMOS |
| Erase Method | — | UV (12V VPP + ultraviolet exposure) |
| Programming Voltage (VPP) | — | 12 V |
| 生命週期狀態 | — | Obsolete (legacy Altera MAX 5000) |