EPM5032SC-25 vs EPM5032LC-15 比較
詳細並排比較 EPM5032SC-25 由 Intel 與 EPM5032LC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032SC-25 | EPM5032LC-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (Erasable/OTP Programmable Logic Device) | — |
| Macrocells | 32 | 32 |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O | 16 | — |
| Total Pin Count | 28 | — |
| 封裝 | PDSO-28 (Plastic DIP Small Outline, SOIC-28 equivalent) | JLCC-28 (windowed ceramic) |
| Speed Grade | -25 | — |
| Propagation Delay (tpd) | 25 ns | — |
| Maximum Counter Frequency (fCNT) | 91 MHz | — |
| Supply Voltage (VCC) | 5 V (typical, 4.5 V to 5.5 V) | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, UV-erasable or OTP | CMOS EPROM, 1.0 um process |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - legacy Altera part; verify with distributor] | Non-compliant (contains Pb, ceramic-windowed package) |
| Programming Method | Altera programming hardware (legacy iMPACT or MAX+PLUS II) | — |
| Architecture | — | PAL-type AND/OR with PIA |
| Usable Gates | — | 600 |
| Logic Array Blocks (LABs) | — | 4 |
| Bidirectional I/O Pins | — | 16 |
| Maximum Operating Frequency | — | 83.3 MHz |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Programmability | — | UV-Erasable / OTP |
| 工作溫度 | — | 0C to +70C (commercial) |