EPM5064JC-1 vs EPM5128JC 比較
詳細並排比較 EPM5064JC-1 由 Altera 與 EPM5128JC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5064JC-1 | EPM5128JC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD / CPLD |
| Macro Cells | 64 | — |
| Usable Gates | 1250 (typical) | — |
| Logic Elements | 128 (Logic Array Blocks) | Programmable AND/OR/XOR array |
| Maximum Operating Frequency | 33.3 MHz (fCNT) | — |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: tPD typical/max in ns] | — |
| Supply Voltage (VCC) | 5 V nominal (4.75 V – 5.25 V) | 5 V (typical) |
| Process Technology | 0.8 µm CMOS | CMOS EPROM |
| Programmable Pins | 36 (typical I/O, 44-pin PLCC) | — |
| Dedicated Inputs | [DATA_NEEDED: dedicated input count] | 8 |
| 封裝 | 44-pin PLCC (J-lead, windowed ceramic) | — |
| 安裝類型 | Surface Mount (PLCC socket recommended) | Surface Mount (PLCC socket or solder) |
| 工作溫度 | 0 °C to +70 °C (commercial, -JC suffix) | Commercial 0C to +70C |
| Erasure Method | UV-erasable through quartz window | — |
| Programming Method | Altera Logic Programmer + MasterBlaster/ByteBlasterMV | — |
| JTAG Boundary Scan | Not supported (classic MAX architecture) | — |
| RoHS 狀態 | Non-compliant (windowed ceramic, contains Pb in glass frit) | [DATA_NEEDED: RoHS status - legacy part] |
| Military/Avionics SMD | 5962-01-417-3750 (QML variant: EPM5064JM/883) | — |
| Product Family | — | MAX 5000 |
| Macrocell Count | — | 128 |
| Propagation Delay (tPD) | — | 35 ns |
| 腳位數 | — | 68 |
| Package Type | — | PLCC-68 (JLCC) ceramic, J-leaded |
| User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Configuration Memory | — | UV-erasable EPROM (windowed package) |
| Programming Interface | — | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Boundary Scan | — | JTAG IEEE 1149.1 (family feature) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |