EPM5064LC-2 vs EPM5064JI-1 比較
詳細並排比較 EPM5064LC-2 由 Altera 與 EPM5064JI-1 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5064LC-2 | EPM5064JI-1 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Device Family | MAX 5000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | — |
| Logic Elements per LAB | 16 | — |
| Number of Inputs | 36 (7 dedicated + 28 I/O) | — |
| Number of I/O Pins | 28 | — |
| Number of Flip-Flops | 28 | — |
| Propagation Delay (tPD) | 45 ns | [DATA_NEEDED: combinational tPD from datasheet] |
| Maximum Internal Frequency | 40 MHz | — |
| Process Technology | CMOS, OTP EPROM (UV-erasable base) | CMOS, UV-erasable |
| Programmable Polarity | Yes | — |
| Programmable Output Enable | Yes, per macrocell | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| 工作溫度 | -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] | [DATA_NEEDED: commercial vs industrial grade temp range] |
| 封裝 | PLCC-44 (J-Lead, plastic) | 68-pin PLCC (windowed ceramic) |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: not specified in source] | [DATA_NEEDED: not stated in provided data] |
| Programming Method | Altera byte-wide / JTAG programmer | — |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| User I/O Pins | — | [DATA_NEEDED: user I/O count from datasheet] |
| Logic Elements | — | [DATA_NEEDED: total logic elements] |
| 供應電壓 | — | 5 V |
| Speed Grade | — | JI-1 (commercial, -10/-12/-15 family) |
| Programmability | — | UV-erasable (windowed package) |
| Data Retention | — | 25 years (per MAX 5000 datasheet) |