EPM5128LC2 vs EPM5192-1LC 比較
詳細並排比較 EPM5128LC2 由 Altera 與 EPM5192-1LC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5128LC2 | EPM5192-1LC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 192 |
| Logic Array Blocks (LABs) | 8 | 4 |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Global Clock Inputs | 1 dedicated | — |
| Propagation Delay (tPD) | 45 ns | — |
| Supply Voltage (VCC) | 5 V | — |
| Process Technology | CMOS EPROM | UV EPROM, erasable windowless |
| Configuration Memory | On-chip EPROM (non-volatile) | — |
| Boundary Scan | JTAG / IEEE 1149.1 | — |
| 工作溫度 | -40 C to +85 C (extended commercial) | 0C to +70C (commercial) |
| 封裝 | PGA (Pin Grid Array, ceramic) | 64-pin Ceramic J-Lead Chip Carrier (LC) |
| 安裝類型 | Through-Hole / Socketed | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic windowless package, lead-bearing termination) |
| Usable Gates | — | 3,750 |
| User I/O Pins | — | 64 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Propagation Delay (tpd) | — | [DATA_NEEDED: -1 speed grade tpd in ns] |
| 供應電壓 | — | 5 V |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |