EPM5130WC-1AA vs EPM5130QC-1 比較
詳細並排比較 EPM5130WC-1AA 由 Altera 與 EPM5130QC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5130WC-1AA | EPM5130QC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Macrocell Count | 128 | — |
| Number of Logic Array Blocks | 8 (typical for MAX 5130) | — |
| Propagation Delay (tPD, max) | 40 ns | — |
| Maximum Toggle Frequency (fCNT) | 50 MHz | — |
| Maximum Clock Frequency (fMAX) | [DATA_NEEDED: fMAX exact value] | — |
| Dedicated Inputs | 19 | — |
| I/O Pins | 48 | — |
| Total Inputs (incl. I/O feedback) | 68 | — |
| Total Outputs | 48 | — |
| Process Technology | 5 V CMOS, UV-erasable | CMOS |
| 封裝 | Windowed Ceramic WQFP (AA suffix) | PQFP-100 (windowed ceramic) |
| 工作溫度 | [DATA_NEEDED: commercial or industrial temp grade] | Commercial (0 C to +70 C) |
| Supply Voltage (VCC) | 5 V nominal | — |
| Programming Method | UV erase + EPROM programming | — |
| RoHS 狀態 | unknown (legacy package, likely non-compliant) | [DATA_NEEDED: rohs status] |
| Logic-to-Pin Ratio | Highest in-class per Altera marketing literature | — |
| Family | — | MAX 5000 |
| Product Type | — | UV-Erasable / OTP Complex PLD (CPLD) |
| Logic Cells / Macrocells | — | 128 macrocells |
| Usable Gates (marketing) | — | 5130 gates |
| Speed Grade | — | -1 |
| Terminal Pitch | — | 0.635 mm |
| Configuration Memory | — | UV-Erasable EPROM |
| 供應電壓 | — | 5 V (single) |
| Programmable Polarity | — | Yes (per macrocell) |
| Boundary Scan / JTAG | — | Per MAX 5000 family |
| 安裝類型 | — | Surface Mount |