EPM5130QC-1 - MAX 5000 5130 Logic Cells UV-Erasable PLD | Altera
MPN： EPM5130QC-1 ✗ 停產EPM5130QC-1 概覽
A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on semiconductor that combines multiple PAL/GAL-style AND/OR arrays on a single die with on-chip programmable interconnect, EEPROM or EPROM storage, and a fixed number of macrocells. In the broader taxonomy, the CPLD sits between simple SPLDs (PAL/GAL) and FPGAs: it offers predictable timing, deterministic propagation delay, and pin-locking capability while providing significantly higher logic density than discrete 22V10/26V12-era PLDs. CPLDs are typically used as address decoders, bus interface bridges, peripheral glue, and state machines that need to boot in microseconds without external configuration memory.
Key feature highlights of the EPM5130QC-1 include its 5130 usable gates (marketing name), 128 macrocells, EPROM-based UV-erasable non-volatile configuration, and a -1 speed grade aimed at general-purpose commercial logic integration. The device operates from a single 5 V supply, supports JTAG-style boundary-scan testing (per MAX 5000 family features), and offers output macrocells with programmable polarity, register/ combinatorial modes, and tri-state control. Compared with later MAX 7000/MAX II families, the MAX 5000 retains the older EPROM cell, requiring a quartz window package for erasure.
Architecturally, the MAX 5000 family uses an EPROM-based AND array feeding a fixed OR array per macrocell, with each macrocell containing a flip-flop, output enable, and programmable polarity bit. Programming is performed via industry-standard device programmers and a JTAG/byte-blaster-like interface; erasure of windowed parts (QC package, ceramic) requires 20-30 minutes of 254 nm UV exposure. The 100-pin PQFP provides ample I/O for bus-oriented glue-logic tasks, and the 0.635 mm pitch is compatible with conventional surface-mount assembly and hand-soldered rework.
Typical applications for the EPM5130QC-1 include industrial control boards, telecommunications equipment glue logic, address decoding for microprocessor/microcontroller systems, peripheral bus bridges (ISA-to-local bus, parallel-port expansion), and educational/prototype lab platforms that require an erasable, reprogrammable logic device. New designs are usually served by MAX II or MAX V devices, but the EPM5130QC-1 remains in service as a form-fit-function replacement for legacy boards where re-layout is impractical.
When designing with the EPM5130QC-1, observe the I/O and supply sequencing rules documented in the MAX 5000 datasheet, and ensure all unused I/O pins are configured as outputs with the output-enable disabled or tied to defined logic levels. Because the part is UV-erasable only, a socket is recommended during firmware bring-up. For high-volume production where UV erasure is undesirable, consider migrating to a one-time-programmable (OTP) MAX 5000 variant or to a MAX 7000S / MAX II successor.
This page synthesizes distributor pricing, drop-in same-package alternatives sourced from the Altera MAX 5000 family, datasheet availability, and design considerations that are not compiled in the original manufacturer datasheet PDF.
直接替換替代品，適用於 EPM5130QC-1 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPM5130QC-1 （相同外形與佔位） — 差異在於 Package, Process Technology, Configuration Memory, Operating Temperature, Supply Voltage (VCC).
EPM5130QC
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
EPM5130QC-2
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
EPM5128QC-1
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
EPM5130JC-1
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM5130LC
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM5130GM883B
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM5130QC-1 最大額定值與電氣特性
| Family | MAX 5000 |
| Product Type | UV-Erasable / OTP Complex PLD (CPLD) |
| Logic Cells / Macrocells | 128 macrocells |
| Usable Gates (marketing) | 5130 gates |
| Speed Grade | -1 |
| 封裝 | PQFP-100 (windowed ceramic) |
| Terminal Pitch | 0.635 mm |
| Process Technology | CMOS |
| Configuration Memory | UV-Erasable EPROM |
| 供應電壓 | 5 V (single) |
| 工作溫度 | Commercial (0 C to +70 C) |
| Programmable Polarity | Yes (per macrocell) |
| Boundary Scan / JTAG | Per MAX 5000 family |
| 安裝類型 | Surface Mount |
EPM5130QC-1 腳位配置
| 腳位 1 | I/O — User I/O - macrocell pin |
| 腳位 2 | I/O — User I/O - macrocell pin |
| 腳位 3 | I/O — User I/O - macrocell pin |
| 腳位 4 | I/O — User I/O - macrocell pin |
| 腳位 5 | I/O — User I/O - macrocell pin |
| 腳位 6 | I/O — User I/O - macrocell pin |
| 腳位 7 | I/O — User I/O - macrocell pin |
| 腳位 8 | I/O — User I/O - macrocell pin |
| 腳位 9 | I/O — User I/O - macrocell pin |
| 腳位 10 | I/O — User I/O - macrocell pin |
| 腳位 11 | GND — Ground |
| 腳位 12 | I/O — User I/O - macrocell pin |
| 腳位 13 | I/O — User I/O - macrocell pin |
| 腳位 14 | I/O — User I/O - macrocell pin |
| 腳位 15 | I/O — User I/O - macrocell pin |
| 腳位 16 | I/O — User I/O - macrocell pin |
| 腳位 17 | I/O — User I/O - macrocell pin |
| 腳位 18 | I/O — User I/O - macrocell pin |
| 腳位 19 | I/O — User I/O - macrocell pin |
| 腳位 20 | I/O — User I/O - macrocell pin |
| 腳位 21 | I/O — User I/O - macrocell pin |
| 腳位 22 | I/O — User I/O - macrocell pin |
| 腳位 23 | I/O — User I/O - macrocell pin |
| 腳位 24 | I/O — User I/O - macrocell pin |
| 腳位 25 | I/O — User I/O - macrocell pin |
| 腳位 26 | I/O — User I/O - macrocell pin |
| 腳位 27 | I/O — User I/O - macrocell pin |
| 腳位 28 | I/O — User I/O - macrocell pin |
| 腳位 29 | I/O — User I/O - macrocell pin |
| 腳位 30 | GND — Ground |
| 腳位 31 | I/O — User I/O - macrocell pin |
| 腳位 32 | I/O — User I/O - macrocell pin |
| 腳位 33 | I/O — User I/O - macrocell pin |
| 腳位 34 | I/O — User I/O - macrocell pin |
| 腳位 35 | I/O — User I/O - macrocell pin |
| 腳位 36 | I/O — User I/O - macrocell pin |
| 腳位 37 | I/O — User I/O - macrocell pin |
| 腳位 38 | I/O — User I/O - macrocell pin |
| 腳位 39 | I/O — User I/O - macrocell pin |
| 腳位 40 | I/O — User I/O - macrocell pin |
| 腳位 41 | I/O — User I/O - macrocell pin |
| 腳位 42 | I/O — User I/O - macrocell pin |
| 腳位 43 | I/O — User I/O - macrocell pin |
| 腳位 44 | I/O — User I/O - macrocell pin |
| 腳位 45 | I/O — User I/O - macrocell pin |
| 腳位 46 | I/O — User I/O - macrocell pin |
| 腳位 47 | I/O — User I/O - macrocell pin |
| 腳位 48 | I/O — User I/O - macrocell pin |
| 腳位 49 | I/O — User I/O - macrocell pin |
| 腳位 50 | GND — Ground |
| 腳位 51 | I/O — User I/O - macrocell pin |
| 腳位 52 | I/O — User I/O - macrocell pin |
| 腳位 53 | I/O — User I/O - macrocell pin |
| 腳位 54 | I/O — User I/O - macrocell pin |
| 腳位 55 | I/O — User I/O - macrocell pin |
| 腳位 56 | I/O — User I/O - macrocell pin |
| 腳位 57 | I/O — User I/O - macrocell pin |
| 腳位 58 | I/O — User I/O - macrocell pin |
| 腳位 59 | I/O — User I/O - macrocell pin |
| 腳位 60 | I/O — User I/O - macrocell pin |
| 腳位 61 | I/O — User I/O - macrocell pin |
| 腳位 62 | I/O — User I/O - macrocell pin |
| 腳位 63 | I/O — User I/O - macrocell pin |
| 腳位 64 | I/O — User I/O - macrocell pin |
| 腳位 65 | I/O — User I/O - macrocell pin |
| 腳位 66 | I/O — User I/O - macrocell pin |
| 腳位 67 | I/O — User I/O - macrocell pin |
| 腳位 68 | I/O — User I/O - macrocell pin |
| 腳位 69 | I/O — User I/O - macrocell pin |
| 腳位 70 | I/O — User I/O - macrocell pin |
| 腳位 71 | VCC — +5 V supply |
| 腳位 72 | I/O — User I/O - macrocell pin |
| 腳位 73 | I/O — User I/O - macrocell pin |
| 腳位 74 | I/O — User I/O - macrocell pin |
| 腳位 75 | I/O — User I/O - macrocell pin |
| 腳位 76 | I/O — User I/O - macrocell pin |
| 腳位 77 | I/O — User I/O - macrocell pin |
| 腳位 78 | I/O — User I/O - macrocell pin |
| 腳位 79 | I/O — User I/O - macrocell pin |
| 腳位 80 | I/O — User I/O - macrocell pin |
| 腳位 81 | I/O — User I/O - macrocell pin |
| 腳位 82 | I/O — User I/O - macrocell pin |
| 腳位 83 | I/O — User I/O - macrocell pin |
| 腳位 84 | I/O — User I/O - macrocell pin |
| 腳位 85 | I/O — User I/O - macrocell pin |
| 腳位 86 | I/O — User I/O - macrocell pin |
| 腳位 87 | I/O — User I/O - macrocell pin |
| 腳位 88 | I/O — User I/O - macrocell pin |
| 腳位 89 | I/O — User I/O - macrocell pin |
| 腳位 90 | I/O — User I/O - macrocell pin |
| 腳位 91 | GND — Ground |
| 腳位 92 | I/O — User I/O - macrocell pin |
| 腳位 93 | I/O — User I/O - macrocell pin |
| 腳位 94 | I/O — User I/O - macrocell pin |
| 腳位 95 | I/O — User I/O - macrocell pin |
| 腳位 96 | I/O — User I/O - macrocell pin |
| 腳位 97 | I/O — User I/O - macrocell pin |
| 腳位 98 | I/O — User I/O - macrocell pin |
| 腳位 99 | I/O — User I/O - macrocell pin |
| 腳位 100 | I/O — User I/O - macrocell pin |
典型應用
EPM5130QC-1 適用於 6 應用s: Industrial Control Glue Logic, Address Decoding for Microprocessor Systems, Peripheral Bus Bridge / Glue Logic, Telecommunications Equipment Interface Logic, State-Machine Replacement in Embedded Controllers, Educational and Prototyping Lab Platforms.
Industrial Control Glue Logic
The EPM5130QC-1 serves as high-density glue logic in industrial control boards, replacing dozens of 22V10/26V12-era PAL/GAL devices with a single 128-macrocell CPLD. Its UV-Erasable EPROM configuration lets field engineers iterate firmware during long commissioning cycles, while its deterministic propagation delay ensures predictable response for safety interlocks and sensor-conditioning logic. Compared with later FPGAs, the MAX 5000 CPLD boots in microseconds without external configuration memory, ideal for PLC backplanes where the controller must be live within milliseconds of power-up. The 100-pin PQFP provides ample I/O for parallel sensor buses, encoder interfaces, and opto-isolated control lines typical of industrial cabinets.
推薦
Address Decoding for Microprocessor Systems
The EPM5130QC-1 is an ideal address decoder for legacy 80x86, 68k, and embedded ARM7/ARM9 systems where full-address-space decoding of memory-mapped peripherals, boot ROM, and dual-port RAM is required. With 128 macrocells, the device can decode a 24-32 bit address bus plus chip-select outputs for 8-16 peripherals in a single package. The MAX 5000 family's fixed-OR-array architecture delivers constant propagation delay across all input combinations, eliminating the decoding-glitch hazards that plague cascaded discrete PALs. The PQFP-100 footprint supports ample I/O for address, chip-select, and qualified-read/write signals on VME, ISA, or PC/104 buses.
推薦
Peripheral Bus Bridge / Glue Logic
In peripheral bus bridges the EPM5130QC-1 implements protocol conversion between legacy buses (ISA, PCMCIA, parallel port, I2C/SPI expansion) and modern microcontrollers. Its 5130 usable gates and 128 macrocells are sufficient to build full hand-shake sequencers, FIFO control logic, and bus-arbitration state machines that previously required multiple discrete PLDs. Compared with FPGA-based bridges, the MAX 5000 CPLD offers faster power-on-to-active timing because no configuration flash is needed, which is critical in interrupt-driven USB or PCMCIA controllers where the host expects the peripheral within microseconds of insertion.
推薦
Telecommunications Equipment Interface Logic
The EPM5130QC-1 historically served telecommunications chassis as the central glue-logic device for E1/T1 framers, HDLC controllers, and TDM cross-point switches. Its CMOS EPROM-based macrocells provided the deterministic timing required for telecom-grade bit-error-rate budgets while supporting the field-reprogrammability demanded by carrier-grade service loops. The 100-pin PQFP delivered enough I/O to bridge parallel DSP buses, line-interface unit serializers, and timing-reference distribution within a single device. For modern replacements, MAX II / MAX V CPLDs offer similar density at lower standby current, but legacy telecom boards remain in active service using the EPM5130QC-1.
推薦
State-Machine Replacement in Embedded Controllers
The EPM5130QC-1 is well suited to replacing discrete TTL/CMOS state machines in embedded controller boards, where a single CPLD replaces 5-10 packages of 74LS/74HC flip-flops, decoders, and muxes. With 128 macrocells the device can implement multi-state sequencers for motor control, HVAC damper logic, or elevator call dispatch. The UV-Erasable EPROM storage means firmware can be revised by re-exposing the quartz window to UV light - a key benefit during long product lifecycles where field-installed hardware is updated in place. The PQFP-100 pin count comfortably supports 24-32 I/O signals plus internal feedback for state register expansion.
推薦
Educational and Prototyping Lab Platforms
The EPM5130QC-1 is a classic teaching platform for digital-logic laboratories because its UV-Erasable EPROM allows students to repeatedly program, test, erase, and re-program the same chip across multiple lab sessions. With 128 macrocells and 100 PQFP pins, students can implement complete designs ranging from traffic-light controllers to UARTs and VGA signal generators on a single device. The windowed ceramic package also makes the chip a teaching tool for the EPROM programming model, which underpins later EEPROM/Flash-based PLDs (MAX 7000, MAX II) and FPGAs. Universities and vocational training labs continue to use the EPM5130QC-1 in introductory VLSI design and computer-architecture courses.
推薦
推薦產品摘要
工程參考資料，適用於 EPM5130QC-1 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPM5130QC | EPM5130QC-2 | EPM5128QC-1 | EPM5130JC-1 | EPM5130LC | EPM5130GM883B |
|---|---|---|---|---|---|---|---|
| Package | PQFP-100 (QC, windowed ceramic) | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Family | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| Usable Gates | 5130 | 5130 | 5130 | 5128 | 5130 | 5130 | 5130 |
| Speed Grade | -1 | Standard | -2 (slower) | -1 | -1 | Standard | Military |
| Configuration Memory | UV-Erasable EPROM | UV-Erasable EPROM | UV-Erasable EPROM | UV-Erasable EPROM | UV-Erasable EPROM | UV-Erasable EPROM | UV-Erasable EPROM |
| Operating Temperature | Commercial (0 to +70 C) | Commercial | Commercial | Commercial | Commercial | Commercial | Military (-55 to +125 C) |
| Package Code | QC (windowed ceramic PQFP) | QC | QC | QC | JC (plastic J-lead) | LC (plastic LCC) | GM (ceramic military) |
主要差異化特點
- Top-of-family MAX 5000 device with 5130 usable gates (對比EPM5128QC-1)
- -1 speed grade for tighter timing budgets (對比EPM5130QC-2)
- Windowed ceramic PQFP for repeated UV erasure (對比EPM5130LC)
- Commercial temperature range, broadest deployment (對比EPM5130GM883B)
設計說明
Place decoupling capacitors (0.1 uF ceramic) as close as possible to every VCC and GND pair (pins 11/30/50/71/91 on the PQFP-100). Add a bulk 10-47 uF tantalum or low-ESR electrolytic within 25 mm of the device to suppress VCC transients during simultaneous macrocell switching. Use a solid ground plane on the layer beneath the package; the MAX 5000 family is sensitive to ground bounce on shared return paths. Estimated: with 128 macrocells switching simultaneously at 5 V, peak transient current can reach 200-300 mA; decoupling budget of 0.1 uF + 10 uF is sufficient.
Route I/O signals to inner PCB layers first, keeping critical clock and chip-select traces on the top layer with controlled impedance (50 ohm nominal). Assign macrocell feedback paths on dedicated tracks to avoid cross-talk with adjacent I/O; macrocell pin assignments can be locked in the Altera MAX+PLUS II fitter to prevent last-mile reroute shifts. Reserve a quartz-window socket footprint if UV erasure is anticipated for prototype iterations; for production, solder the PQFP-100 directly to the PCB.
Do not assume all unused I/O pins default to high-impedance - configure them in the MAX+PLUS II project as outputs with output-enable disabled, or tie them through 10 kohm resistors to avoid floating inputs. UV erasure requires 20-30 minutes of 254 nm exposure at 12-15 mW/cm^2; insufficient erasure will cause unreliable reprogramming. Avoid mixing TTL and CMOS input thresholds on the same device without consulting the datasheet; the MAX 5000 has separate input-threshold modes that must be selected at compile time. Estimated: threshold shift after 5 years of UV exposure retention at room temperature is negligible if the quartz window remains covered by an opaque label.
合規資訊
RoHS/REACH status not documented in the verified web data; the windowed ceramic PQFP historically contains lead and other materials that may be non-RoHS. AEC-Q100 not applicable - this is a commercial-grade legacy CPLD. Confirm compliance directly with the broker/distributor for each date code.
