EPM5192AGC vs EPM51929C 比較

詳細並排比較 EPM5192AGC 由 Altera 與 EPM51929C 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM5192AGC EPM51929C
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family MAX 5000 (High-Speed, High-Density MAX 5000 Devices) —
Device Type UV-Erasable / OTP Complex PLD (EPLD) EPLD (Erasable Programmable Logic Device)
Macrocells 192 —
Logic Density High-density (per MAX 5000 family definition) [DATA_NEEDED: usable gates]
Architecture CMOS, sum-of-products with macrocell output logic Multi-array matrix (PAL-based macrocells)
Process Technology CMOS —
封裝 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) —
Speed Grade Suffix C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) —
工作溫度 [DATA_NEEDED: operating temperature range] Commercial (0C to +70C)
Programmability UV-erasable (windowed package) / One-Time-Programmable (windowless variant) UV-erasable, JEDEC fuse map
Security Bit Programmable security bit (per MAX 5000 family) —
供應電壓 [DATA_NEEDED: VCC nominal and tolerance] [DATA_NEEDED: VCC range]
安裝類型 Through-hole (Pin Grid Array) Surface Mount or Through-Hole (package dependent)
RoHS 狀態 Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) unknown
Lifecycle Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) —
Programming Support MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers —
Device Family — MAX 5000
Number of Macrocells — [DATA_NEEDED: macrocell count]
腳位數 — [DATA_NEEDED: pin count]
Package Type — [DATA_NEEDED: package suffix - C denotes commercial temperature grade]
Technology — CMOS EPROM
Propagation Delay — [DATA_NEEDED: tpd specification]
Maximum Toggle Frequency — [DATA_NEEDED: fmax]
Lead-Free — unknown
MSL 等級 — [DATA_NEEDED]

資料表與資源

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