EPM5192AJC84-15 vs EPM5192AJI84-20 比較
詳細並排比較 EPM5192AJC84-15 由 Altera 與 EPM5192AJI84-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 Obsolete規格比較
| 參數 | EPM5192AJC84-15 | EPM5192AJI84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable / OTP Complex PLD |
| Macrocells | 192 | — |
| Propagation Delay (tpd) | 15 ns | — |
| Maximum Clock Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V nominal (4.5 V to 5.5 V) |
| Technology | CMOS, UV-erasable EPROM | — |
| 封裝 | 84-pin PLCC (J84C) windowed ceramic | — |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | — |
| Programming Method | UV-erase + EPROM programming (windowed package) | — |
| Logic Blocks | 16 Logic Array Blocks (LABs) | — |
| I/O Pins | [DATA_NEEDED: user I/O count] | — |
| RoHS 狀態 | Non-compliant (contains Pb, ceramic windowed package) | [DATA_NEEDED: RoHS status of EPM5192AJI84-20] |
| Process Technology | CMOS EPROM | CMOS |
| Device Family | — | MAX 5000 (EPM5192) |
| Logic Cells / Macrocells | — | 192 macrocells |
| Propagation Delay (tPD) | — | 33 ns |
| Maximum Frequency (fCNT) | — | 66.7 MHz |
| Operating Temperature Grade | — | Industrial |
| Package Code | — | WQCCJ (JEDEC) |
| Package Type | — | 84-pin J-bend Ceramic Chip Carrier (PLCC-84, JI) |
| Terminal Form | — | J-Bend |
| Number of Terminals | — | 84 |
| Programmability | — | UV-erasable window + OTP |
| 腳位數 | — | 84 |
| 生命週期狀態 | — | Obsolete (legacy Altera MAX 5000) |