EPM5192AJC84-15 vs EPM5192ALC84-15 比較
詳細並排比較 EPM5192AJC84-15 由 Altera 與 EPM5192ALC84-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
EPM5192AJC84-15 Obsolete規格比較
| 參數 | EPM5192AJC84-15 | EPM5192ALC84-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD / UV-Erasable / OTP Complex PLD |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 15 ns | — |
| Maximum Clock Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 4.75 V to 5.25 V (nominal 5 V) |
| Technology | CMOS, UV-erasable EPROM | — |
| 封裝 | 84-pin PLCC (J84C) windowed ceramic | 84-pin PLCC (QCCJ, J-bend ceramic) |
| 安裝類型 | Surface Mount | — |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | — |
| Programming Method | UV-erase + EPROM programming (windowed package) | — |
| Logic Blocks | 16 Logic Array Blocks (LABs) | — |
| I/O Pins | [DATA_NEEDED: user I/O count] | — |
| RoHS 狀態 | Non-compliant (contains Pb, ceramic windowed package) | — |
| Process Technology | CMOS EPROM | CMOS (EPROM-based) |
| Device Family | — | MAX 5000 (EPM5192) |
| Dedicated Inputs | — | 7 |
| User I/O Pins | — | 64 |
| Propagation Delay (tPD) | — | 15 ns |
| Propagation Delay (Industry Variant) | — | 25 ns (per MicrochipUSA listing) |
| Programmability | — | UV-erasable window / OTP |
| Operating Temperature Grade | — | Commercial |
| Terminal Form | — | J-BEND |
| Package Code | — | QCCJ |
| Package Shape | — | SQUARE |
| Architecture | — | Programmable Logic Array + Macrocell Registers + PIA interconnect |