EPM5192ALC84-15 vs EPM5192ALM84-20 比較
詳細並排比較 EPM5192ALC84-15 由 Altera 與 EPM5192ALM84-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192ALC84-15 | EPM5192ALM84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 5000 (EPM5192) | — |
| Device Type | CPLD / UV-Erasable / OTP Complex PLD | UV-Erasable/OTP Complex PLD (CPLD) |
| Macrocells | 192 | 192 |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | 64 |
| Propagation Delay (tPD) | 15 ns | 33 ns |
| Propagation Delay (Industry Variant) | 25 ns (per MicrochipUSA listing) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Process Technology | CMOS (EPROM-based) | CMOS |
| Programmability | UV-erasable window / OTP | — |
| 封裝 | 84-pin PLCC (QCCJ, J-bend ceramic) | 84-pin PQCC (PLCC), J-Lead, surface-mount |
| Operating Temperature Grade | Commercial | — |
| Terminal Form | J-BEND | — |
| Package Code | QCCJ | — |
| Package Shape | SQUARE | — |
| Architecture | Programmable Logic Array + Macrocell Registers + PIA interconnect | — |
| Family | — | MAX 5000 |
| Total Inputs | — | 71 (64 I/O + 7 dedicated) |
| 最大時脈頻率 | — | 66.7 MHz |
| Programmable Security Bit | — | Yes |
| Logic Voltage Compatibility | — | 5 V TTL |
| Configuration Memory | — | EPROM (UV-erasable, windowless in this package) |
| 工作溫度 | — | [DATA_NEEDED: commercial/industrial/military grade] |
| RoHS 狀態 | — | unknown (legacy Altera part) |