EPM5192AQI100-20 vs EPM5192AQC100-20 比較

詳細並排比較 EPM5192AQI100-20 由 Altera 與 EPM5192AQC100-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM5192AQI100-20 EPM5192AQC100-20
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family MAX 5000 EPLD —
Device Series EPM5192 —
Technology CMOS, UV-erasable EPROM —
Propagation Delay 20 ns (speed grade -20) —
Logic Array Blocks (LABs) 12 —
Interconnect Programmable Interconnect Array (PIA) —
Macrocell Count 192 —
Dedicated Inputs 7 —
I/O Pins 64 bidirectional —
封裝 100-pin PQFP (R-PQFP-G100) 100-lead PQFP (R-PQFP-G100)
JEDEC Package Outline R-PQFP-G100 —
工作溫度 Industrial grade ("I" suffix) —
安裝類型 Surface Mount (PQFP) Surface Mount (PQFP)
Architecture Classic EPLD, deterministic timing —
Design Tool Altera MAX+PLUS II (legacy) —
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
供應電壓 [DATA_NEEDED: VCC range] 5 V (typical, MAX 5000 family)
Device Family — MAX 5000
Product Type — Complex Programmable Logic Device (CPLD)
Macrocells — 192
Maximum Operating Frequency — 66.7 MHz
Propagation Delay (tpd) — 33 ns
Terminal Pitch — 0.65 mm
Process Technology — CMOS
Programming Technology — UV-Erasable / One-Time-Programmable (OTP)
工作溫度範圍 — [DATA_NEEDED: operating temperature range]
I/O Count — [DATA_NEEDED: usable I/O count]
Logic Array Blocks — Multiple LABs (per MAX 5000 architecture)
Lead-Free — [DATA_NEEDED: lead-free status]
MSL 等級 — [DATA_NEEDED: MSL rating]

資料表與資源

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