EPM5192AQI100-20 vs EPM5192AQI100-15 比較
詳細並排比較 EPM5192AQI100-20 由 Altera 與 EPM5192AQI100-15 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM5192AQI100-20 - MAX 5000 192-Macrocell EPLD, 20ns, PQFP-100 | Altera
EPM5192AQI100-20 Obsolete規格比較
| 參數 | EPM5192AQI100-20 | EPM5192AQI100-15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 EPLD | MAX 5000 |
| Device Series | EPM5192 | — |
| Technology | CMOS, UV-erasable EPROM | CMOS, EPROM-based (UV-erasable on windowed versions, OTP on this part) |
| Propagation Delay | 20 ns (speed grade -20) | — |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Macrocell Count | 192 | — |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 64 bidirectional | — |
| 封裝 | 100-pin PQFP (R-PQFP-G100) | PQFP-100 (R-PQFP-G100), 100-pin Plastic Quad Flat Pack |
| JEDEC Package Outline | R-PQFP-G100 | — |
| 工作溫度 | Industrial grade ("I" suffix) | — |
| 安裝類型 | Surface Mount (PQFP) | — |
| Architecture | Classic EPLD, deterministic timing | — |
| Design Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| 供應電壓 | [DATA_NEEDED: VCC range] | [DATA_NEEDED: VCC typical value] |
| Series | — | MAX® 5000 EPLD |
| Device Type | — | OT PLD (One-Time-Programmable EPLD), CMOS |
| Macrocells | — | 192 |
| Programmable I/O Lines | — | 64 |
| Total Logical Inputs | — | 72 |
| Propagation Delay (tpd) | — | 15 ns (speed grade -15) |
| Propagation Delay (max datasheet) | — | 25 ns |
| Maximum Internal Frequency | — | 83.3 MHz |
| Operating Temperature Grade | — | Industrial (-40C to +85C) - 'I' suffix |
| Programming Method | — | JTAG via Altera programming hardware (ByteBlasterMV, USB-Blaster) |