EPM5192GI vs EPM5192JC-ES 比較
詳細並排比較 EPM5192GI 由 Altera 與 EPM5192JC-ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192GI | EPM5192JC-ES |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (EPLD) |
| Technology | CMOS EPROM (UV-erasable / OTP) | CMOS |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 16 (12 macrocells per LAB) | 12 |
| User I/O Pins | 64 | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] |
| Dedicated Inputs | 7 | — |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 55 ns | — |
| Maximum Internal Frequency (fCNT) | 33.3 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | — |
| 工作溫度 | -40 C to +85 C (Industrial) | [DATA_NEEDED: operating temperature range for ES grade] |
| Package Type | 84-pin PGA (Pin Grid Array), ceramic with quartz window | — |
| Programmable | UV-erasable (windowed) and OTP variants | — |
| 安裝類型 | Through-hole (PGA) | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: not confirmed in verified web data] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Configuration Memory | — | EPROM (UV-erasable, one-time programmable for JC-ES) |
| 封裝 | — | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) |
| Programming | — | Altera MAX+PLUS II or compatible programmer |
| 供應電壓 | — | [DATA_NEEDED: VCC nominal] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| Note | — | Datasheet source: Altera MAX 5000 family document, 52 pages |