EPM5192JC-2 vs EPM5192GC84-1 比較
詳細並排比較 EPM5192JC-2 由 Altera 與 EPM5192GC84-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JC-2 | EPM5192GC84-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-erasable Programmable Logic Device (PLD) | UV-Erasable/OTP Complex PLD (CPLD) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 45 ns | 40 ns (speed grade -1) |
| 最大時脈頻率 | 40 MHz | 50 MHz |
| Process Technology | CMOS | — |
| 封裝 | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) | 84-pin PGA (Pin Grid Array), WPGA code |
| 安裝類型 | Surface Mount | Through-hole (PGA socket) |
| Number of Terminals | 84 | — |
| Programming Method | UV-erase / EPROM | UV erasure (quartz window) + EPROM programmer |
| 工作溫度範圍 | [DATA_NEEDED: operating temperature range] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Compliant (per third-party distributor listing) |
| Family | — | MAX 5000 |
| Technology | — | CMOS (EPROM-cell based) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Total Inputs / Outputs | — | 72 inputs / 64 outputs |
| Architecture | — | Shared input/clock and shared product terms |
| Temperature Grade | — | Commercial |
| Logic Element Type | — | Macrocells with AND/OR array |