EPM5192JI-2 vs EPM5192IC-1 比較
詳細並排比較 EPM5192JI-2 由 Altera 與 EPM5192IC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JI-2 | EPM5192IC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Usable Gates | 5000 | 3750 |
| Dedicated Inputs | 12 | 7 |
| Flip-Flops | 192 | — |
| Speed Grade | -2 | — |
| 封裝 | JLCC-68 (J-Lead Ceramic) | 68-pin ceramic J-lead (IC-1 suffix) |
| 工作溫度 | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Programming Technology | UV-Erasable EPROM | — |
| Architecture | Sum-of-products with Programmable Interconnect Array (PIA) | — |
| 供應電壓 | 5 V (typical) | — |
| Process Technology | CMOS EPROM | — |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | Non-compliant (ceramic JLCC, contains lead) | — |
| 生命週期狀態 | Obsolete (legacy Altera MAX 5000 family) | — |
| I/O Pins | — | 64 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (max, -1 speed grade) |
| Counter Frequency (fCNT) | — | 76.9 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Technology | — | CMOS, UV-erasable, in-system programmable |
| Programming Interface | — | JTAG / IEEE Std 1149.1 boundary scan |
| Security Bit | — | Yes (design protection) |
| Supply Current (Icc, typical) | — | [DATA_NEEDED: Icc] mA |
| Output Drive Current (IOH/IOL) | — | [DATA_NEEDED: IOH/IOL] mA |