EPM5192LC-2 vs EPM5192LC-45 比較
詳細並排比較 EPM5192LC-2 由 Altera 與 EPM5192LC-45 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC-2 | EPM5192LC-45 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | — |
| Dedicated Input Pins | 7 | — |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 45 ns (typical, -2 speed grade) | — |
| Maximum Internal Frequency | 50 MHz | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS | — |
| 封裝 | PQCC-84 (PLCC-84, J-lead, surface mount) | — |
| Programming | Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) | — |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | 0C to +70C (commercial) |
| 供應電壓 | 5 V (typical MAX 5000 family) | 5 V |
| RoHS 狀態 | [DATA_NEEDED: pre-RoHS legacy part — likely non-RoHS] | [DATA_NEEDED: RoHS status] |
| Series | — | EPM5192 |
| Logic Elements | — | 192 macrocells |
| Maximum Operating Frequency | — | 100 MHz |
| Pin-to-Pin Delay (tPD) | — | 45 ns |
| Dedicated Inputs | — | [DATA_NEEDED: dedicated input count] |
| Programmable I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Configuration Memory | — | UV-erasable EPROM / OTP |
| Technology | — | EPROM-based CMOS |
| Package Type | — | LCC (Leaded Ceramic Chip Carrier) with UV window |
| Package Code | — | LC |
| Speed Grade | — | -45 (45 ns tPD) |
| 安裝類型 | — | Surface Mount (LCC) |
| Datasheet Page Count | — | 52 pages |