EPM5192LC-M205A vs EPM5192LC-25 比較
詳細並排比較 EPM5192LC-M205A 由 Altera 與 EPM5192LC-25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC-M205A | EPM5192LC-25 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Dedicated Inputs | 7 | — |
| I/O Pins | 64 | — |
| Propagation Delay (tPD) | 55 ns | — |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS EPROM (UV-erasable / OTP) | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Global Clock Inputs | 1 | — |
| 工作溫度 | [DATA_NEEDED: operating temperature grade] | 0C to +70C (commercial) |
| Package Type | 205-pin (M205A) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Unknown (legacy ceramic package typically non-RoHS) |
| Configuration Memory | UV-erasable / OTP EPROM | Non-volatile EPROM (on-chip) |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements | — | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) |
| Pin-to-Pin Delay (tPD) | — | 25 ns |
| Speed Grade | — | -25 (25 ns) |
| 封裝 | — | JLCC-84 (ceramic J-lead chip carrier) |
| Programmable Technology | — | UV-erasable / OTP (EPROM-based) |
| Programming Interface | — | JTAG / Altera programming hardware (legacy) |
| 供應電壓 | — | 5 V (typical, MAX 5000) |
| I/O Standard | — | TTL-compatible |
| Manufacturer | — | Altera Corporation (now Intel PSG) |