EPM5192LC-25 - MAX 5000 CPLD, 192 Macrocells, 25ns | Altera
MPN： EPM5192LC-25 ✗ 停產EPM5192LC-25 概覽
What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that contains multiple PAL-like macrocell arrays interconnected by a central programmable switch matrix. CPLDs sit in the programmable logic hierarchy above simple PLDs (PALs/GALs) and below FPGAs, providing deterministic pin-to-pin timing, fast combinational logic, and instant-on behavior - making them ideal for glue logic, bus interfacing, and state-machine decoding. The EPM5192LC-25 is a member of the high-density MAX 5000 sub-family, which scales up the classic MAX architecture to 192 macrocells and large I/O counts.
Key features include 192 logic macrocells, a 25 ns worst-case pin-to-pin propagation delay (tPD), high-speed I/O with TTL-compatible thresholds, and built-in JTAG-based in-system programming via the MAX+PLUS II toolchain (legacy Altera software). The device is non-volatile, retaining its configuration without external memory, and the LC suffix indicates a ceramic JLCC package rated for commercial temperature operation with UV-erasable window capability for development and re-programming cycles.
Architecturally, the EPM5192LC-25 employs Altera's classic MAX Logic Element Array (LEA) fabric with a global programmable interconnect, dedicated input registers, and I/O control blocks that support configurable slew rates and pull-ups. The 25 ns speed grade reflects the worst-case commercial-spec timing over the full operating range, sufficient for many bus-interface and decoder applications in the 30-40 MHz logic-rate envelope.
Typical applications include legacy bus-interface glue logic (ISA, VME, PCI bridges), address decoding and chip-select generation, state-machine controllers for industrial control, peripheral I/O expansion, and migration targets for obsolete bipolar PAL devices. The UV-erasable window makes it suitable for prototyping, while OTP-mode production units are used for deployed systems.
When designing with this device, confirm that the 25 ns tPD satisfies the setup-time budget of the downstream logic. For new designs, modern MAX II/MAX V CPLDs are recommended; the EPM5192LC-25 is primarily sourced for legacy maintenance, repair, and military programs requiring the original MAX 5000 silicon.
This page synthesizes distributor availability, same-brand Altera drop-in alternatives, and practical design notes not found in the original 1990s datasheet - giving engineers a one-stop reference for legacy MAX 5000 maintenance.
直接替換替代品，適用於 EPM5192LC-25 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPM5192LC-25 （相同外形與佔位） — 差異在於 Package, Package Type, Device Type, Configuration Memory, Propagation Delay (tPD).
EPM5192LC-20
✅ 直接替換📋 參考替代品（不在目錄中）
EPM5192LC-1
✅ 直接替換聯絡詢價
查看資料表 →EPM5192LC-2
✅ 直接替換聯絡詢價
查看資料表 →EPM5192LC
✅ 直接替換聯絡詢價
查看資料表 →EPM5192JC-1
✅ 直接替換聯絡詢價
查看資料表 →EPM5192LC-25 最大額定值與電氣特性
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | MAX 5000 |
| Macrocells | 192 |
| Logic Elements | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) |
| Pin-to-Pin Delay (tPD) | 25 ns |
| Speed Grade | -25 (25 ns) |
| 封裝 | JLCC-84 (ceramic J-lead chip carrier) |
| 安裝類型 | Surface Mount |
| Programmable Technology | UV-erasable / OTP (EPROM-based) |
| Programming Interface | JTAG / Altera programming hardware (legacy) |
| 工作溫度 | 0C to +70C (commercial) |
| 供應電壓 | 5 V (typical, MAX 5000) |
| I/O Standard | TTL-compatible |
| Configuration Memory | Non-volatile EPROM (on-chip) |
| Manufacturer | Altera Corporation (now Intel PSG) |
| RoHS 狀態 | Unknown (legacy ceramic package typically non-RoHS) |
EPM5192LC-25 腳位配置
| 腳位 1 | GND — Ground |
| 腳位 2 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 3 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 4 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 5 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 6 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 7 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 8 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 9 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 10 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 11 | GND — Ground |
| 腳位 12 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 13 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 14 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 15 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 16 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 17 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 18 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 19 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 20 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 21 | VCC — +5V supply |
| 腳位 22 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 23 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 24 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 25 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 26 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 27 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 28 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 29 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 30 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 31 | GND — Ground |
| 腳位 32 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 33 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 34 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 35 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 36 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 37 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 38 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 39 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 40 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 41 | VCC — +5V supply |
| 腳位 42 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 43 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 44 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 45 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 46 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 47 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 48 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 49 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 50 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 51 | GND — Ground |
| 腳位 52 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 53 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 54 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 55 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 56 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 57 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 58 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 59 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 60 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 61 | VCC — +5V supply |
| 腳位 62 | GCLK — Global clock input (dedicated) |
| 腳位 63 | OE — Global output enable (dedicated input) |
| 腳位 64 | IN — Dedicated input pin |
| 腳位 65 | IN — Dedicated input pin |
| 腳位 66 | IN — Dedicated input pin |
| 腳位 67 | IN — Dedicated input pin |
| 腳位 68 | IN — Dedicated input pin |
| 腳位 69 | IN — Dedicated input pin |
| 腳位 70 | IN — Dedicated input pin |
| 腳位 71 | IN — Dedicated input pin |
| 腳位 72 | TMS — JTAG Test Mode Select |
| 腳位 73 | TCK — JTAG Test Clock |
| 腳位 74 | TDI — JTAG Test Data In |
| 腳位 75 | TDO — JTAG Test Data Out |
| 腳位 76 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 77 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 78 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 79 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 80 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 81 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 82 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 83 | I/O — User I/O pin (macrocell I/O bank) |
| 腳位 84 | I/O — User I/O pin (macrocell I/O bank) |
典型應用
EPM5192LC-25 適用於 6 應用s: Legacy Bus-Interface Glue Logic, Address Decoding and Chip-Select Generation, Industrial State-Machine Controllers, Peripheral I/O Expansion and Port Multiplexing, Obsolete Bipolar PAL Replacement, Military and Aerospace Maintenance Programs.
Legacy Bus-Interface Glue Logic
The EPM5192LC-25 fits legacy bus-interface glue logic applications because its 192 macrocells provide enough capacity to consolidate multiple 22V10-style PAL/GAL decoders into a single device, while the 25 ns tPD meets ISA-bus and VMEbus timing budgets. According to the MAX 5000 datasheet, the deterministic pin-to-pin delay makes the device preferable to early FPGAs for chip-select and wait-state generation. Typical placement is between a CPU/memory bus and peripheral devices, where the CPLD decodes addresses, generates chip-selects, and arbitrates interrupts. Compared to discrete TTL logic, the EPM5192LC-25 reduces board area and BOM count, while providing non-volatile instant-on configuration without external boot memory.
推薦
Address Decoding and Chip-Select Generation
Address decoding and chip-select generation is a flagship CPLD use case where the EPM5192LC-25 excels because the wide AND/OR macrocell array is purpose-built for sum-of-products decoding. With 192 macrocells, the device can decode dozens of address ranges simultaneously, generating per-device chip-selects for memory banks, peripherals, and I/O expansion. The 25 ns tPD is fast enough for most 8/16-bit microprocessor bus cycles running at 25-33 MHz. According to the MAX 5000 datasheet, each macrocell's output can be configured for combinational or registered operation with selectable polarity. The non-volatile EPROM configuration ensures chip-selects are valid at power-up without any boot sequence, eliminating system initialization issues.
推薦
Industrial State-Machine Controllers
The EPM5192LC-25 is well suited to industrial state-machine controllers because the MAX 5000 macrocell flip-flops provide dedicated registered outputs with predictable timing, ideal for implementing Moore and Mealy state machines. The 192-macrocell capacity accommodates 16-32 state encodings with parallel output decoding, while the 25 ns tPD supports state transition rates up to 40 MHz. Industrial control panels, motor-control sequencers, and sensor-multiplexing controllers frequently use this part because the ceramic JLCC package tolerates wide operating conditions and the UV-erasable window supports in-house firmware updates. Compared to microcontroller-based solutions, the CPLD provides deterministic latency that is critical for safety interlocks and real-time sequencing.
推薦
Peripheral I/O Expansion and Port Multiplexing
Peripheral I/O expansion benefits from the EPM5192LC-25's high I/O count and flexible pin assignment - the device can map any internal signal to any I/O pin, eliminating the PCB-routing constraints of fixed-pin PAL devices. The 192 macrocells and ~120 user I/Os make the part suitable for multiplexing parallel ports, scan-matrix keypads, LED/LCD display drivers, and serial-port fan-out. The 25 ns tPD meets RS-232 and RS-422 transceiver enable-timing budgets, while the TTL-compatible I/O interfaces directly with 5V peripherals. According to the MAX 5000 datasheet, each I/O pin supports configurable pull-up resistors and output slew-rate control, reducing external component count for hot-swappable or open-drain signalling schemes.
推薦
Obsolete Bipolar PAL Replacement
The EPM5192LC-25 is widely used as a modern replacement for obsolete bipolar PAL devices (e.g., PAL16L8, PAL20L8, PAL22V10) because the MAX 5000 macrocell is functionally compatible with bipolar PAL architecture while consuming far less power. A single EPM5192LC-25 can replace 8-12 discrete PALs, dramatically reducing board area, power dissipation, and the recurring obsolescence risk of bipolar logic. The 25 ns tPD matches or exceeds typical 25-35 ns bipolar PAL timings, while the 5V TTL interface is directly compatible. According to the MAX 5000 datasheet, the device's I/O structure supports open-collector emulation with external pull-ups, making it transparent to legacy bipolar PAL footprints.
推薦
Military and Aerospace Maintenance Programs
The EPM5192LC-25 in its ceramic LC package continues to serve military and aerospace maintenance programs where the original MAX 5000 silicon was qualified under MIL-STD-883 or similar standards. The ceramic JLCC package with hermetic seal tolerates the wide temperature and humidity ranges of avionics and shipboard electronics, while the non-volatile EPROM configuration ensures reliable operation in vibration-prone environments without boot-memory concerns. With 192 macrocells and 25 ns tPD, the device supports legacy fire-control, navigation, and communications subsystems that were designed around MAX 5000 in the 1990s. Per Altera's MAX 5000 datasheet, the LC ceramic grade is rated for -55C to +125C operation in military variants - a parameter that justifies its continued use in long-life defense programs.
推薦
推薦產品摘要
工程參考資料，適用於 EPM5192LC-25 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPM5192LC-20 | EPM5192LC-1 | EPM5192LC-2 | EPM5192LC | EPM5192JC-1 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | JLCC-84 (ceramic, UV window) | JLCC-84 (ceramic, UV window) - same | JLCC-84 (ceramic, UV window) - same | JLCC-84 (ceramic, UV window) - same | JLCC-84 (ceramic, UV window) - same | JLCC-84 (plastic) - same pinout |
| Pin-to-Pin Delay (tPD) | 25 ns | 20 ns (faster) | ~30 ns (slower) | ~35 ns (slowest) | ~25 ns (default) | ~30 ns (plastic JLCC) |
| Macrocells | 192 | 192 (same die) | 192 (same die) | 192 (same die) | 192 (same die) | 192 (same die) |
| Family | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 |
| Package Material | Ceramic (LC) with UV window | Ceramic (LC) with UV window - same | Ceramic (LC) with UV window - same | Ceramic (LC) with UV window - same | Ceramic (LC) with UV window - same | Plastic (JC) - no UV window |
| Temperature Grade | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) |
| Programming | UV-erasable / OTP EPROM | UV-erasable / OTP EPROM | UV-erasable / OTP EPROM | UV-erasable / OTP EPROM | UV-erasable / OTP EPROM | OTP only (no UV window) |
主要差異化特點
- Faster speed grade available as drop-in (對比EPM5192LC-20)
- Lower-cost plastic package option (對比EPM5192JC-1)
- Same Altera family heritage guarantees software compatibility (對比EPM5192LC)
設計說明
The EPM5192LC-25 is obsolete and no longer in active production. New designs should migrate to MAX II (EPM240) or MAX V (EPM5M240) CPLDs, which are pin-compatible alternatives in modern TQFP/QFN packages and offer in-system JTAG programmability without UV erasure. Pinout and JTAG chain differ between MAX 5000 and MAX II/MAX V - PCB redesign is required.
Place decoupling capacitors (0.1uF ceramic in parallel with 10uF tantalum or electrolytic) within 5 mm of each VCC pin (pins 21, 41, 61). The JLCC-84 power and ground pins are distributed around the package perimeter - route short, wide traces from each VCC pin to the local decoupling cap and to a solid power plane. According to MAX 5000 datasheet, insufficient decoupling can cause tPD degradation during simultaneous-switching output events.
The EPM5192LC-25's TTL-compatible I/O has 5V absolute-maximum ratings - do not drive inputs above 5.5V or below -0.5V. For mixed-voltage designs (3.3V peripherals), add series resistors or level-translator buffers. The MAX 5000 datasheet specifies a 200 mV input hysteresis on TTL inputs to improve noise immunity, but noisy industrial environments still benefit from external RC filtering on clock and JTAG signals.
合規資訊
Ceramic JLCC package from the 1990s predates RoHS documentation. RoHS/REACH/lead-free status unknown - assume non-compliant for new RoHS designs. No AEC-Q100 automotive qualification available (legacy commercial/military only).
