EPM5192LC1 vs EPM5192GC84-1 比較
詳細並排比較 EPM5192LC1 由 Altera 與 EPM5192GC84-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC1 | EPM5192GC84-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Complex PLD (CPLD), UV-erasable/OTP | — |
| Macrocells | 192 | 192 |
| Equivalent Gates | 3750 | — |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | 64 |
| 封裝 | PQCC-84 (JEDEC S-PQCC-J84, 84-lead Plastic Leaded Chip Carrier) | 84-pin PGA (Pin Grid Array), WPGA code |
| Nominal Supply Voltage (VCC) | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| 最大時脈頻率 | 50 MHz | 50 MHz |
| Propagation Delay (tPD) | 40 ns | 40 ns (speed grade -1) |
| Process Technology | CMOS EPROM | — |
| Programming Method | OTP (LC plastic package); UV-erasable equivalents in JC ceramic package | UV erasure (quartz window) + EPROM programmer |
| Operating Temperature (Commercial 'LC') | 0 °C to 70 °C | — |
| 安裝類型 | Surface Mount | Through-hole (PGA socket) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant (per third-party distributor listing) |
| JEDEC Package Code | S-PQCC-J84 | — |
| Product Type | — | UV-Erasable/OTP Complex PLD (CPLD) |
| Technology | — | CMOS (EPROM-cell based) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Total Inputs / Outputs | — | 72 inputs / 64 outputs |
| Architecture | — | Shared input/clock and shared product terms |
| Temperature Grade | — | Commercial |
| Logic Element Type | — | Macrocells with AND/OR array |