EPM5192LC84-2 vs EPM7128ELC84-12 比較
詳細並排比較 EPM5192LC84-2 由 Altera 與 EPM7128ELC84-12 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC84-2 | EPM7128ELC84-12 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 7000 (MAX 7000E series) |
| Device Type | EPLD (UV-Erasable / OTP Complex PLD) | — |
| Macrocells | 192 | 128 |
| 封裝 | 84-pin PLCC (LC) | 84-pin PLCC (J-Lead, QCCJ) |
| Speed Grade | -2 | — |
| 供應電壓 | 5 V (TTL-compatible I/O) | — |
| Technology | CMOS, UV-erasable / OTP | — |
| Logic Elements | AND-OR array with macrocell flip-flops | — |
| Programming Method | Altera legacy programmer (JEDEC bitstream) | — |
| 工作溫度 | Commercial (0C to +70C) | 0C to +70C (commercial) |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket compatible) |
| RoHS 狀態 | Non-compliant (SnPb lead finish typical for this vintage) | Non-compliant (legacy 5V part, SnPb finish) |
| 生命週期狀態 | Obsolete (last Altera MAX 5000 production) | — |
| JTAG Support | Vendor-specific programming interface (pre-IEEE 1532) | — |
| I/O Standard | TTL, 5V CMOS-compatible | — |
| Logic Family | — | CMOS, EEPROM-based |
| Usable Gates | — | 2,500 |
| Logic Array Blocks (LABs) | — | 8 |
| User I/Os | — | 84 |
| Propagation Delay (tpd1) | — | 12 ns |
| Internal Global Clock Frequency | — | 90.9 MHz |
| Setup Time | — | 4.5 ns |
| Supply Voltage (VCCINT / VCCIO) | — | 5 V (4.75 V to 5.25 V) |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| 腳位數 | — | 84 |