EPM570F100A5N vs EPM570F100C5N 比較
詳細並排比較 EPM570F100A5N 由 Altera 與 EPM570F100C5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM570F100A5N | EPM570F100C5N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX II | MAX II |
| Logic Elements | 570 | 570 |
| Macrocells | 440 | — |
| User Flash Memory | 8 Kbits | — |
| Pin-to-Pin Delay (tPD) | 5.4 ns | — |
| Maximum Operating Frequency | 201.1 MHz | — |
| User I/O Pins (max) | 76 | — |
| Global Clock Lines | 4 | — |
| Supply Voltage - Core | 3.3 V | — |
| Supply Voltage - I/O Banks | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Process Technology | 0.18 µm flash | 0.18 micron CMOS |
| 封裝 | 100-ball FBGA | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) |
| 工作溫度 | 0°C to +85°C (commercial) | 0C to 85C (TJ) |
| RoHS 狀態 | Compliant | — |
| Number of Macrocells | — | 440 |
| User I/Os | — | 76 |
| Number of Logic Array Blocks | — | 57 |
| Propagation Delay (tPD) | — | 5.4 ns |
| Supply Voltage - Internal | — | 2.5 V, 3.3 V |
| I/O Standards Supported | — | 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| 安裝類型 | — | Surface Mount |
| 封裝 / 外殼 | — | 100-LBGA (FBGA-100), 11 x 11 mm, 1.0 mm pitch |
| Supplier Device Package | — | 100-FBGA |
| Configuration Memory | — | On-chip Flash (instant-on, non-volatile) |
| In-System Programmability | — | Yes (JTAG, IEEE 1532) |
| User Flash Memory (UFM) | — | 8 Kbit |
| Lead Free / RoHS | — | Yes (per verified data) |