EPM570F100C4N vs EPM570F100I5N 比較

詳細並排比較 EPM570F100C4N 由 Intel 與 EPM570F100I5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Intel
EPM570F100C4N EPM570F100C4N - MAX II CPLD, 440 LEs, 100-FBGA | Intel

EPM570F100C4N - MAX II CPLD, 440 LEs, 100-FBGA | Intel

EPM570F100C4N ✓ 啟用中

規格比較

參數 EPM570F100C4N EPM570F100I5N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family MAX II MAX II
Device Type CPLD (Complex Programmable Logic Device) CPLD (Flash-based)
Logic Elements 440 LE —
Macrocells 440 440
Maximum User I/O 80 —
Pin-to-Pin Delay (tPD1) 5.4 ns —
User Flash Memory 4.4 Kbits 8 Kbits
Configuration Technology Flash (non-volatile, instant-on) —
Operating Voltage (Core) 3.3 V (internal regulator) —
I/O Voltage Support (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V —
封裝 100-FBGA (FineLine BGA) 11 mm x 11 mm 100-ball FineLine BGA (11x11 mm)
工作溫度 0 C to +85 C (commercial) -40C to +100C (Industrial)
安裝類型 Surface Mount (BGA) Surface Mount
JTAG Support Yes (IEEE 1149.1 boundary-scan) —
Hot Socketing Yes Supported
Logic Elements (LEs) — 570
Maximum User I/Os — 76
Maximum Operating Frequency — 304 MHz
Propagation Delay (tPD) — 8.7 ns (max), 5.4 ns (typical)
Supply Voltage (VCCINT) — 2.375 V to 3.6 V
Typical Supply Current (ICC) — 55 mA
I/O Standards Supported — LVCMOS, LVTTL, LVDS, SSTL, HSTL (1.5/1.8/2.5/3.3 V)
Programming Interface — JTAG (IEEE 1149.1), in-system programmable
Global Clocks — 4
Process Technology — CMOS, Flash configuration cell
RoHS 狀態 — Compliant

資料表與資源

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