EPM570M100I5N vs EPM570M100C4N 比較
詳細並排比較 EPM570M100I5N 由 Intel 與 EPM570M100C4N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM570M100I5N | EPM570M100C4N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX II | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | 440 | — |
| Number of Logic Array Blocks | 4 LABs (110 macrocells each) | — |
| Maximum Operating Frequency | 201.1 MHz | — |
| Pin-to-Pin Logic Delay | 5.4 ns | — |
| User I/Os | 76 | 76 |
| User Flash Memory | 8 Kbits | — |
| Process Technology | 0.18 µm CMOS | 0.18 µm 6-layer-metal flash |
| Supply Voltage - Core (VCCINT) | 2.5 V / 3.3 V | — |
| Supply Voltage - I/O (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (banked) | — |
| Package Type | 100-MBGA (Micro FBGA) | — |
| Package Size | 6 x 6 mm, 0.5 mm pitch | — |
| 安裝類型 | Surface Mount | — |
| 工作溫度 | -40°C to +100°C (I5 grade) | 0 °C to +85 °C (commercial, C suffix) |
| Lead-Free / RoHS | Lead Free, RoHS Compliant | — |
| Programmability | In-System via JTAG (IEEE 1149.1), non-volatile | — |
| Design Software | Altera Quartus II / Quartus Prime | — |
| Macrocells | — | 440 |
| Logic Elements (LEs) | — | 570 |
| Pin-to-Pin Logic Delay (tPD) | — | 5.4 ns |
| User Flash Memory (UFM) | — | 8 Kbits |
| 封裝 | — | 100-pin MBGA (Micro FineLine BGA) |
| Supply Voltage (Core) | — | 3.3 V (typical for MAX II) |
| MultiVolt I/O Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Programming Interface | — | JTAG (IEEE 1149.1) ISP |
| Configuration Memory | — | Non-volatile flash (instant-on) |
| RoHS 狀態 | — | Compliant |