EPM570M100I5N vs EPM570M100C5N 比較
詳細並排比較 EPM570M100I5N 由 Intel 與 EPM570M100C5N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM570M100I5N | EPM570M100C5N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX II | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | 440 | — |
| Number of Logic Array Blocks | 4 LABs (110 macrocells each) | — |
| Maximum Operating Frequency | 201.1 MHz | — |
| Pin-to-Pin Logic Delay | 5.4 ns | — |
| User I/Os | 76 | 76 |
| User Flash Memory | 8 Kbits | — |
| Process Technology | 0.18 µm CMOS | 0.18 um, 6-layer-metal flash |
| Supply Voltage - Core (VCCINT) | 2.5 V / 3.3 V | — |
| Supply Voltage - I/O (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (banked) | — |
| Package Type | 100-MBGA (Micro FBGA) | — |
| Package Size | 6 x 6 mm, 0.5 mm pitch | — |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| 工作溫度 | -40°C to +100°C (I5 grade) | — |
| Lead-Free / RoHS | Lead Free, RoHS Compliant | — |
| Programmability | In-System via JTAG (IEEE 1149.1), non-volatile | — |
| Design Software | Altera Quartus II / Quartus Prime | — |
| Series | — | EPM570 |
| Macrocell Count | — | 440 |
| Logic Elements | — | 570 |
| Number of Logic Blocks / Array Blocks | — | [DATA_NEEDED: number of LABs] |
| 腳位數 | — | 100 |
| 封裝 | — | 100-MBGA (FineLine BGA, 6 x 6 mm, 0.5 mm pitch) |
| Maximum Frequency (fMAX) | — | 201.1 MHz |
| Pin-to-Pin Propagation Delay | — | 5.4 ns |
| Operating Supply Voltage (Core) | — | 2.5 V / 3.3 V |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| On-Chip User Flash Memory (UFM) | — | 8 Kbits |
| Programming Interface | — | JTAG (IEEE 1149.1) and ISP |
| 工作溫度範圍 | — | 0 C to +85 C (Commercial) |
| RoHS 狀態 | — | Lead-Free / Compliant |
| Moisture Sensitivity Level | — | [DATA_NEEDED: MSL level] |