EPM570T100A5N vs EPM240T100C5N 比較
詳細並排比較 EPM570T100A5N 由 Altera 與 EPM240T100C5N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM570T100A5N | EPM240T100C5N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Device Family | MAX II | — |
| Logic Elements | 570 | — |
| Macrocells | 440 | — |
| User I/O Pins | 76 | — |
| Number of Logic Array Blocks (LABs) | 57 | — |
| 封裝 | 100-pin TQFP | 100-pin TQFP (T100), 14x14 mm |
| Pin-to-Pin Logic Delay (tPD) | 5.4 ns | — |
| Maximum Internal Frequency | 304 MHz | 201.1 MHz |
| Core Supply Voltage (VCCINT) | 1.8 V (typical) | 2.5 V / 3.3 V |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| User Flash Memory (UFM) | 8 Kbits | — |
| Configuration Memory | On-chip non-volatile flash | — |
| Programming Interface | JTAG (IEEE 1149.1) - ISP | JTAG (IEEE 1149.1) / ISP |
| 工作溫度 | -40 °C to +125 °C (industrial) | 0 °C to +85 °C (commercial, 'C' suffix) |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | Compliant | Compliant (lead-free) |
| Family | — | MAX II |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements (LEs) | — | 240 |
| Equivalent Macrocells | — | 192 |
| On-Chip User Flash | — | 8 Kbits |
| Maximum User I/O Pins | — | 80 |
| Number of I/O Banks | — | 4 |
| Pin-to-Pin Delay (speed grade 5) | — | 4.7 ns |
| Process Technology | — | 0.18 µm, 6-layer-metal flash |