EPM570T100C4 vs EPM570T100C3 比較

詳細並排比較 EPM570T100C4 由 Intel 與 EPM570T100C3 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM570T100C4 EPM570T100C3
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family MAX II MAX II
Logic Elements (LEs) 570 —
Macrocells 440 —
Maximum User I/O Pins (this package) 80 —
Pin-to-Pin Propagation Delay (tPD) 5.4 ns —
User Flash Memory 8 Kbits —
General-Purpose SRAM 4.4 Mbits —
Core Voltage (VCCINT) 1.8 V —
I/O Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) —
封裝 TQFP-100 (T100), 14 x 14 mm 100-pin TQFP (T100), 14×14 mm
工作溫度 0C to +85C (commercial) —
Programming Interface JTAG (IEEE 1149.1) - ISP —
安裝類型 Surface Mount Surface Mount
MSL 等級 [DATA_NEEDED: MSL Level] —
RoHS 狀態 Compliant Compliant
On-chip Oscillator Yes (3.3 MHz / 5.5 MHz selectable) —
Internal Logic Analyzers / ISP JTAG-based in-system programmable, no external boot PROM required —
Device Type — CPLD (Complex Programmable Logic Device)
Logic Elements — 570
Equivalent Macrocells — 440
User I/O Pins — 76 (max)
User Flash Memory (UFM) — 8 Kbits
Maximum Operating Frequency — 304 MHz
Technology Node — 0.18 µm 6-layer-metal flash process
Internal Supply Voltage — 2.5 V / 3.3 V
I/O Voltage Support (MultiVolt) — 1.5 V, 1.8 V, 2.5 V, 3.3 V
Temperature Grade — Commercial (C)
Speed Grade — 3 (fastest C-grade)
Programming — In-System Programmable (ISP) via JTAG (IEEE 1149.1)

資料表與資源

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