EPM570T144I5N vs EPM570T144C5N 比較
詳細並排比較 EPM570T144I5N 由 Intel 與 EPM570T144C5N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM570T144I5N | EPM570T144C5N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | 啟用中 |
| Family | MAX II | MAX II |
| Logic Elements | 570 LE | — |
| Macrocells | 440 | 440 |
| Maximum Pin-to-Pin Delay (tPD1) | 8.7 ns | — |
| Maximum Frequency (fCNT) | 304 MHz | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Supply Voltage - Core (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| 工作溫度 | -40C to +100C (industrial) | 0 °C to +85 °C (commercial, C5 grade) |
| Speed Grade | I5N | — |
| Process Technology | 0.18 um CMOS, 6-layer-metal flash | 0.18 µm 6-layer-metal flash |
| 封裝 | TQFP-144 (22 mm x 22 mm, 0.5 mm pitch) | TQFP-144 (20 × 20 mm, 0.5 mm pitch) |
| 安裝類型 | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | IEEE 1149.1 JTAG (in-system programmable) |
| Boundary-Scan Test | IEEE 1149.1 compliant | — |
| RoHS 狀態 | Compliant | Compliant |
| Series | — | MAX II Device |
| Logic Elements (LEs) | — | 570 |
| User I/Os | — | 116 |
| Internal User Flash Memory | — | 8 Kbit |
| Global Clocks | — | 4 |
| Core Voltage (VCCINT) | — | 1.8 V (typical, internally regulated) |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage, per bank) |
| Maximum User I/O Pins | — | 116 |
| Propagation Delay (tPD) | — | 5.5 ns (typical, [DATA_NEEDED: exact speed grade]) |
| Maximum Frequency (fMAX) | — | 201.1 MHz |
| Configuration Storage | — | On-chip non-volatile flash |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI, LVDS, SSTL (per bank VCCIO) |
| Lead-Free | — | Yes |
| MSL 等級 | — | 3 (per JEDEC J-STD-020) |
| Design Software | — | Intel Quartus II (MAX II device support) |