EPM7128AETC100-7N vs EPM7128AETI100-7N 比較
詳細並排比較 EPM7128AETC100-7N 由 Altera 與 EPM7128AETI100-7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
EPM7128AETI100-7N Obsolete規格比較
| 參數 | EPM7128AETC100-7N | EPM7128AETI100-7N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 7000A | MAX 7000A CPLD |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | — |
| Logic Array Blocks (LABs) | 4 | — |
| User I/Os | 84 | — |
| Propagation Delay (tpd) | 7.5 ns | — |
| Counter Frequency (max) | 129.9 MHz | — |
| Internal Frequency (max) | 250 MHz | — |
| Core Supply Voltage | 3.3 V | — |
| Logic Family | CMOS | — |
| 腳位數 | 100 | — |
| 封裝 | 100-TQFP | 100-pin TQFP (14x14 mm) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0 C to +70 C (Commercial) | -40C to +85C (Industrial) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant |
| Process Technology | 0.30 µm EEPROM CMOS | CMOS EEPROM |
| Series | — | MAX 7000A |
| Number of Usable Gates | — | 2,500 |
| Number of I/O | — | 84 |
| Number of Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tPD max) | — | 7 ns |
| Maximum Operating Frequency (fCNT) | — | 129.9 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Bank Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |