EPM7128AETC144-10 vs EPM7128AETI144-10N 比較
詳細並排比較 EPM7128AETC144-10 由 Altera 與 EPM7128AETI144-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128AETI144-10N - MAX 7000A CPLD, 128 Macrocells, TQFP-144 | Altera
EPM7128AETI144-10N Obsolete規格比較
| 參數 | EPM7128AETC144-10 | EPM7128AETI144-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 7000A | MAX 7000A |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 | 8 |
| Maximum User I/Os | 36 | — |
| Pin-to-pin Logic Delay (tPD) | 10 ns | — |
| Maximum Internal Counter Frequency | 98 MHz | — |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Voltage Tolerance | 2.5 V / 3.3 V / 5 V | — |
| 工作溫度 | 0C to +70C (Commercial) | -40C to +85C (industrial) |
| 封裝 | 144-pin TQFP (also referred to as LQFP-144) | TQFP-144 (144-pin) |
| Programming Interface | JTAG (IEEE Std. 1149.1) and ByteBlaster | — |
| Non-volatile Memory | EEPROM, instant-on | — |
| Global Clocks / Global OE | 2 / 2 | — |
| 安裝類型 | Surface Mount | Surface Mount |
| MSL 等級 | MSL 3 (per JEDEC J-STD-020) | 3 |
| RoHS 狀態 | [DATA_NEEDED: rohs status from manufacturer] | Compliant |
| Maximum User I/O Pins | — | 100 |
| Propagation Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V nominal) |
| Programming Technology | — | EEPROM (in-system programmable) |
| JTAG Interface | — | IEEE Std 1149.1 BST compliant |
| Process Technology | — | 0.35 µm CMOS EEPROM |
| Speed Grade | — | -10 (10 ns tPD) |
| Operating Frequency (fCNT) | — | [DATA_NEEDED: fCNT counter frequency] |