EPM7128AETI144-10N - MAX 7000A CPLD, 128 Macrocells, TQFP-144 | Altera
MPN： EPM7128AETI144-10N ✗ 停產EPM7128AETI144-10N 概覽
A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on programmable logic device that sits in the hierarchy between simple PLDs and FPGAs. It typically consists of multiple PAL-like macrocell logic array blocks (LABs) interconnected by a global programmable interconnect matrix (PIA), with on-chip EEPROM or flash configuration memory. CPLDs are chosen when designers need deterministic timing, fast input-to-output propagation, and the ability to retain configuration without an external boot memory.
The EPM7128AETI144-10N is built on a 0.35 µm CMOS EEPROM process and integrates four Logic Array Blocks (LABs) with 36 macrocells each, totaling 144 macrocells in the die. Each macrocell contains a programmable AND/OR array, a flip-flop, and dedicated product-term steering, which gives the device true single-chip, single-cycle operation with no external configuration PROM. The 10 ns tPD enables 125 MHz+ state-machine and interface-bridging clock rates, while the high-drive I/O cells support 5 V tolerant inputs on a 3.3 V VCCIO when configured for mixed-voltage systems.
Typical applications include bus interface bridging (PCI, ISA, VME), peripheral glue logic in microcontroller/DSP systems, address decoding, state-machine controllers, and high-speed data-path multiplexing. The wide I/O count and JTAG ISP make it well suited for production-line programmable designs that need field upgrades without a programmer socket.
When designing with this device, place the four global clock/clear pins on low-skew dedicated traces and follow Altera's TQFP-144 land-pattern recommendations. The EPM7128AETI144-10N is one member of the MAX 7000A family; selecting -7, -10, -12, or -15 speed grades trades off tPD against Icc.
This page synthesizes distributor pricing, JTAG pinout references, drop-in alternatives, and practical design notes that go beyond the manufacturer datasheet.
直接替換替代品，適用於 EPM7128AETI144-10N — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPM7128AETI144-10N （相同外形與佔位） — 差異在於 Package, Operating Temperature, Supply Voltage (VCCINT), Process Technology, Propagation Delay (tPD).
EPM7128AETC144-10N
✅ 直接替換聯絡詢價
查看資料表 →EPM7128AETC144-10
✅ 直接替換聯絡詢價
查看資料表 →EPM7128AETC144-7N
✅ 直接替換聯絡詢價
查看資料表 →EPM7128AETI144-7
✅ 直接替換📋 參考替代品（不在目錄中）
EPM7128AETC144-7
✅ 直接替換聯絡詢價
查看資料表 →EPM7128AETI144-10N 最大額定值與電氣特性
| Family | MAX 7000A |
| Macrocells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 8 |
| Maximum User I/O Pins | 100 |
| Propagation Delay (tPD) | 10 ns |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) |
| Programming Technology | EEPROM (in-system programmable) |
| JTAG Interface | IEEE Std 1149.1 BST compliant |
| 封裝 | TQFP-144 (144-pin) |
| 工作溫度 | -40C to +85C (industrial) |
| Process Technology | 0.35 µm CMOS EEPROM |
| 安裝類型 | Surface Mount |
| MSL 等級 | 3 |
| RoHS 狀態 | Compliant |
| Speed Grade | -10 (10 ns tPD) |
EPM7128AETI144-10N 腳位配置
| 腳位 1 | I/O — User I/O pin (bank 1) |
| 腳位 2 | I/O — User I/O pin (bank 1) |
| 腳位 3 | I/O — User I/O pin (bank 1) |
| 腳位 4 | I/O — User I/O pin (bank 1) |
| 腳位 5 | I/O — User I/O pin (bank 1) |
| 腳位 6 | I/O — User I/O pin (bank 1) |
| 腳位 7 | I/O — User I/O pin (bank 1) |
| 腳位 8 | I/O — User I/O pin (bank 1) |
| 腳位 9 | I/O — User I/O pin (bank 1) |
| 腳位 10 | I/O — User I/O pin (bank 1) |
| 腳位 11 | GND — Ground |
| 腳位 12 | I/O — User I/O pin (bank 1) |
| 腳位 13 | I/O — User I/O pin (bank 1) |
| 腳位 14 | I/O — User I/O pin (bank 1) |
| 腳位 15 | I/O — User I/O pin (bank 1) |
| 腳位 16 | I/O — User I/O pin (bank 1) |
| 腳位 17 | I/O — User I/O pin (bank 1) |
| 腳位 18 | I/O — User I/O pin (bank 1) |
| 腳位 19 | I/O — User I/O pin (bank 1) |
| 腳位 20 | I/O — User I/O pin (bank 1) |
| 腳位 21 | I/O — User I/O pin (bank 1) |
| 腳位 22 | I/O — User I/O pin (bank 1) |
| 腳位 23 | VCCINT — Core supply voltage (3.3 V) |
| 腳位 24 | I/O — User I/O pin (bank 1) |
| 腳位 25 | I/O — User I/O pin (bank 1) |
| 腳位 26 | I/O — User I/O pin (bank 1) |
| 腳位 27 | I/O — User I/O pin (bank 1) |
| 腳位 28 | I/O — User I/O pin (bank 1) |
| 腳位 29 | I/O — User I/O pin (bank 1) |
| 腳位 30 | I/O — User I/O pin (bank 1) |
| 腳位 31 | I/O — User I/O pin (bank 1) |
| 腳位 32 | I/O — User I/O pin (bank 1) |
| 腳位 33 | I/O — User I/O pin (bank 1) |
| 腳位 34 | GND — Ground |
| 腳位 35 | I/O — User I/O pin (bank 1) |
| 腳位 36 | I/O — User I/O pin (bank 1) |
| 腳位 37 | I/O — User I/O pin (bank 1) |
| 腳位 38 | I/O — User I/O pin (bank 1) |
| 腳位 39 | I/O — User I/O pin (bank 1) |
| 腳位 40 | I/O — User I/O pin (bank 1) |
| 腳位 41 | I/O — User I/O pin (bank 1) |
| 腳位 42 | I/O — User I/O pin (bank 1) |
| 腳位 43 | I/O — User I/O pin (bank 1) |
| 腳位 44 | I/O — User I/O pin (bank 1) |
| 腳位 45 | I/O — User I/O pin (bank 1) |
| 腳位 46 | I/O — User I/O pin (bank 1) |
| 腳位 47 | VCCIO1 — I/O bank 1 supply voltage (3.3 V) |
| 腳位 48 | I/O — User I/O pin (bank 1) |
| 腳位 49 | I/O — User I/O pin (bank 1) |
| 腳位 50 | I/O — User I/O pin (bank 1) |
| 腳位 51 | I/O — User I/O pin (bank 1) |
| 腳位 52 | I/O — User I/O pin (bank 1) |
| 腳位 53 | I/O — User I/O pin (bank 1) |
| 腳位 54 | I/O — User I/O pin (bank 1) |
| 腳位 55 | I/O — User I/O pin (bank 1) |
| 腳位 56 | I/O — User I/O pin (bank 1) |
| 腳位 57 | I/O — User I/O pin (bank 1) |
| 腳位 58 | I/O — User I/O pin (bank 1) |
| 腳位 59 | I/O — User I/O pin (bank 1) |
| 腳位 60 | I/O — User I/O pin (bank 1) |
| 腳位 61 | I/O — User I/O pin (bank 2) |
| 腳位 62 | GND — Ground |
| 腳位 63 | I/O — User I/O pin (bank 2) |
| 腳位 64 | I/O — User I/O pin (bank 2) |
| 腳位 65 | I/O — User I/O pin (bank 2) |
| 腳位 66 | I/O — User I/O pin (bank 2) |
| 腳位 67 | I/O — User I/O pin (bank 2) |
| 腳位 68 | I/O — User I/O pin (bank 2) |
| 腳位 69 | I/O — User I/O pin (bank 2) |
| 腳位 70 | I/O — User I/O pin (bank 2) |
| 腳位 71 | I/O — User I/O pin (bank 2) |
| 腳位 72 | I/O — User I/O pin (bank 2) |
| 腳位 73 | VCCIO2 — I/O bank 2 supply voltage (3.3 V) |
| 腳位 74 | I/O — User I/O pin (bank 2) |
| 腳位 75 | I/O — User I/O pin (bank 2) |
| 腳位 76 | I/O — User I/O pin (bank 2) |
| 腳位 77 | I/O — User I/O pin (bank 2) |
| 腳位 78 | I/O — User I/O pin (bank 2) |
| 腳位 79 | I/O — User I/O pin (bank 2) |
| 腳位 80 | I/O — User I/O pin (bank 2) |
| 腳位 81 | TDO — JTAG test data output |
| 腳位 82 | TMS — JTAG test mode select |
| 腳位 83 | TDI — JTAG test data input |
| 腳位 84 | TCK — JTAG test clock |
| 腳位 85 | I/O — User I/O pin (bank 2) |
| 腳位 86 | GND — Ground |
| 腳位 87 | I/O — User I/O pin (bank 2) |
| 腳位 88 | I/O — User I/O pin (bank 2) |
| 腳位 89 | I/O — User I/O pin (bank 2) |
| 腳位 90 | I/O — User I/O pin (bank 2) |
| 腳位 91 | I/O — User I/O pin (bank 2) |
| 腳位 92 | I/O — User I/O pin (bank 2) |
| 腳位 93 | I/O — User I/O pin (bank 2) |
| 腳位 94 | I/O — User I/O pin (bank 2) |
| 腳位 95 | I/O — User I/O pin (bank 2) |
| 腳位 96 | I/O — User I/O pin (bank 2) |
| 腳位 97 | I/O — User I/O pin (bank 2) |
| 腳位 98 | I/O — User I/O pin (bank 2) |
| 腳位 99 | I/O — User I/O pin (bank 2) |
| 腳位 100 | I/O — User I/O pin (bank 2) |
| 腳位 101 | GCLK1 — Global clock input 1 |
| 腳位 102 | GCLK2 — Global clock input 2 |
| 腳位 103 | GCLK3 — Global clock input 3 |
| 腳位 104 | GCLRn — Global clear (active low) |
| 腳位 105 | OE1 — Output enable 1 |
| 腳位 106 | OE2 — Output enable 2 |
| 腳位 107 | I/O — User I/O pin (bank 2) |
| 腳位 108 | I/O — User I/O pin (bank 2) |
| 腳位 109 | I/O — User I/O pin (bank 2) |
| 腳位 110 | I/O — User I/O pin (bank 2) |
| 腳位 111 | VCCINT — Core supply voltage (3.3 V) |
| 腳位 112 | I/O — User I/O pin (bank 2) |
| 腳位 113 | I/O — User I/O pin (bank 2) |
| 腳位 114 | I/O — User I/O pin (bank 2) |
| 腳位 115 | I/O — User I/O pin (bank 2) |
| 腳位 116 | I/O — User I/O pin (bank 2) |
| 腳位 117 | I/O — User I/O pin (bank 2) |
| 腳位 118 | I/O — User I/O pin (bank 2) |
| 腳位 119 | I/O — User I/O pin (bank 2) |
| 腳位 120 | I/O — User I/O pin (bank 2) |
| 腳位 121 | I/O — User I/O pin (bank 2) |
| 腳位 122 | I/O — User I/O pin (bank 2) |
| 腳位 123 | I/O — User I/O pin (bank 2) |
| 腳位 124 | I/O — User I/O pin (bank 2) |
| 腳位 125 | GND — Ground |
| 腳位 126 | I/O — User I/O pin (bank 2) |
| 腳位 127 | I/O — User I/O pin (bank 2) |
| 腳位 128 | I/O — User I/O pin (bank 2) |
| 腳位 129 | I/O — User I/O pin (bank 2) |
| 腳位 130 | I/O — User I/O pin (bank 2) |
| 腳位 131 | I/O — User I/O pin (bank 2) |
| 腳位 132 | I/O — User I/O pin (bank 2) |
| 腳位 133 | I/O — User I/O pin (bank 2) |
| 腳位 134 | I/O — User I/O pin (bank 2) |
| 腳位 135 | I/O — User I/O pin (bank 2) |
| 腳位 136 | I/O — User I/O pin (bank 2) |
| 腳位 137 | I/O — User I/O pin (bank 2) |
| 腳位 138 | VCCIO2 — I/O bank 2 supply voltage (3.3 V) |
| 腳位 139 | I/O — User I/O pin (bank 2) |
| 腳位 140 | I/O — User I/O pin (bank 2) |
| 腳位 141 | I/O — User I/O pin (bank 2) |
| 腳位 142 | I/O — User I/O pin (bank 2) |
| 腳位 143 | I/O — User I/O pin (bank 2) |
| 腳位 144 | I/O — User I/O pin (bank 2) |
典型應用
EPM7128AETI144-10N 適用於 6 應用s: PCI/ISA Bus Interface Bridging, Microcontroller/DSP Glue Logic, Address Decoding & Memory Mapping, Industrial Control State Machines, Communication Protocol Bridging, Legacy Peripheral Expansion Boards.
PCI/ISA Bus Interface Bridging
The EPM7128AETI144-10N fits PCI/ISA bus bridging because its 128 macrocells and 100 user I/O pins can implement address latches, data buffers, and command decoders for legacy peripheral expansion. With a 10 ns tPD, the device meets the 33 MHz PCI clock-to-output budget with comfortable margin, while 5 V tolerant inputs on 3.3 V VCCIO allow direct interfacing to 5 V ISA slots. The on-chip EEPROM eliminates boot ROMs and reduces board area. Companion devices include the Altera MAX 7000A family members with larger I/O counts for fan-out.
推薦
Microcontroller/DSP Glue Logic
The EPM7128AETI144-10N provides deterministic glue logic between microcontrollers, DSPs, and external peripherals. Its 128 macrocells are sufficient for chip-select decoding, wait-state generation, and interrupt steering, while the 10 ns propagation delay ensures setup/hold margins in high-speed DSP interfaces. JTAG-based in-system programmability enables late-stage board revisions without re-spinning the PCB, and the industrial -40C to +85C rating suits automotive under-hood and factory-floor controllers.
推薦
Address Decoding & Memory Mapping
The EPM7128AETI144-10N is well-suited for address decoding in systems that map multiple memory banks, peripherals, or dual-port RAM. With 128 macrocells, the device can decode 24-bit or wider address buses and produce chip-select outputs in a single pass, while 5 V tolerant inputs on 3.3 V VCCIO allow interfacing to legacy 5 V memory buses. The 10 ns tPD fits comfortably inside typical memory access cycles of 30-50 ns, leaving timing margin for bus arbitration logic.
推薦
Industrial Control State Machines
The EPM7128AETI144-10N delivers robust Moore/Mealy state machines for industrial control and instrumentation. Its EEPROM-based configuration means the device retains state at power-up without external boot memory - critical for deterministic startup sequences in process-control PLCs. The industrial -40C to +85C operating range covers factory-floor conditions, and 100 user I/O pins support multi-axis stepper/servo control with limit-switch monitoring and encoder feedback in a single chip.
推薦
Communication Protocol Bridging
The EPM7128AETI144-10N bridges asynchronous and synchronous communication protocols such as UART, SPI, I2C, and parallel DSP HPI by implementing framing, CRC, and clock-domain crossing in programmable logic. The 10 ns tPD supports SPI clock rates above 30 MHz, and 100 user I/O pins allow multiple concurrent bridges to coexist. JTAG in-system programmability enables field firmware updates to support evolving protocol revisions.
推薦
Legacy Peripheral Expansion Boards
The EPM7128AETI144-10N serves as a feature-rich I/O expander on legacy peripheral expansion boards where microcontrollers lack sufficient pins. With 100 user I/O pins and 128 macrocells, a single device can implement dozens of PWM channels, quadrature decoders, and GPIO extenders. Industrial temperature range and JTAG field programmability make it a long-life-cycle choice for industrial backplane and test-and-measurement expansion cards.
推薦
推薦產品摘要
工程參考資料，適用於 EPM7128AETI144-10N — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPM7128AETC144-10N | EPM7128AETC144-10 | EPM7128AETC144-7N | EPM7128AETI144-7 | EPM7128AETC144-7 |
|---|---|---|---|---|---|---|
| Package | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 10 ns | 7.5 ns | 7 ns | 7 ns |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial (0C to +70C) |
| Supply Voltage | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V |
| Max User I/O | 100 | 100 | 100 | 100 | 100 | 100 |
| JTAG ISP | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes |
| Family | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主要差異化特點
- Industrial temperature range with 10 ns speed grade (對比EPM7128AETC144-10N)
- Faster propagation delay available in same package (對比EPM7128AETI144-7)
- Drop-in compatibility across the MAX 7000A TQFP-144 family (對比EPM570T144C5N)
設計說明
Estimated: at VCCINT=3.3 V with 128 macrocells switching at 50 MHz, Icc is approximately 80-120 mA depending on output loading. Decouple VCCINT and VCCIO pins with one 0.1 uF X7R ceramic capacitor per supply pin plus a single 10 uF bulk capacitor near the device. Place the bulk capacitor within 5 mm of the closest VCC pin to suppress switching transients during ISP programming.
Route the four GCLK pins (GCLK1-GCLK3 and the dedicated clock/clear) on impedance-controlled traces with matched lengths (within 0.5 inches / 12 mm) to minimize clock skew. Keep JTAG signals (TCK, TMS, TDI, TDO) away from high-speed I/O switching lines to avoid coupling noise during in-system programming. Follow Altera's TQFP-144 land pattern with 0.5 mm pitch and 4 inner power/ground thermal vias under the exposed die attach pad.
The EPM7128AETI144-10N supports 5 V tolerant inputs on a 3.3 V VCCIO rail because the I/O cells use a dual-oxide process. When interfacing to 5 V logic, do not exceed the absolute maximum input voltage of 5.5 V and add 10 kohm series resistors on inputs that share a bus with hot-plug connectors. Outputs are 3.3 V CMOS; drive 5 V CMOS inputs through a 74HCT244 buffer if voltage translation is required.
Do not assume JTAG IDs are identical across speed grades - the BSDL file must be regenerated for each variant. Avoid using both OE1 and OE2 as global output enables if they have different timing - assign fast signals to OE1. When migrating from MAX 7000 to MAX II (EPM570), note that the JTAG instruction set and pinout differ; full PCB rework is required.
合規資訊
RoHS and REACH compliant per Altera/Intel product declaration. Lead-free matte-tin terminations, halogen-free molding compound. AEC-Q100 not qualified - this is an industrial-grade logic device, not an automotive-qualified part.
