EPM7128AETC144-10N vs EPM7128AETC144-7N 比較
詳細並排比較 EPM7128AETC144-10N 由 Intel 與 EPM7128AETC144-7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128AETC144-7N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel / Altera
EPM7128AETC144-7N ✓ 啟用中規格比較
| 參數 | EPM7128AETC144-10N | EPM7128AETC144-7N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX 7000A | MAX 7000A |
| Number of Macros | 128 | — |
| Logic Gates | 2,500 usable gates | 2500 (2.5K gates) |
| Number of I/O Pins | 100 (max user I/O) | — |
| Propagation Delay (tPD) | 10 ns (grade -10) | — |
| Internal Frequency | Up to 250 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Standards | 2.5 V / 3.3 V / 5 V multiVolt | — |
| Configuration Memory | CMOS EEPROM (non-volatile) | — |
| JTAG Support | IEEE 1149.1 compliant boundary-scan | — |
| 封裝 | 144-pin TQFP (T144) | 144-pin TQFP |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | Yes |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 128 |
| User I/Os | — | 36 (in 144-pin TQFP) |
| Maximum Operating Frequency | — | 129.9 MHz |
| Pin-to-Pin Delay | — | 7.5 ns |
| Propagation Delay (tpd) | — | 7.5 ns |
| Process Technology | — | CMOS, EEPROM-based |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| Boundary-Scan Test | — | IEEE Std 1149.1 (JTAG) |
| Pin-Compatible With | — | MAX 7000S 5.0V family (144-pin TQFP) |