EPM7128SQC100-7F vs EPM7128SQC100-10N 比較
詳細並排比較 EPM7128SQC100-7F 由 Altera 與 EPM7128SQC100-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7128SQC100-7F | EPM7128SQC100-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 啟用中 |
| Family | MAX 7000S | MAX 7000 |
| Logic Elements / Blocks | 8 LABs | — |
| Number of Macrocells | 128 | — |
| Number of Usable Gates | 2,500 | — |
| Maximum Operating Frequency | 125 MHz | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Number of User I/O | 84 | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) | 5 V (4.75 V to 5.25 V) |
| Programmable Type | In-System Programmable (ISP), EEPROM | — |
| JTAG Boundary-Scan | Yes (IEEE 1149.1 BST) | — |
| Open-Drain Output Option | Yes | — |
| 工作溫度 | 0 °C to 70 °C (Commercial) | -40C to +85C (industrial) |
| 封裝 | 100-pin PQFP (SQC100), surface-mount | 100-pin PQFP (BQFP) |
| 安裝類型 | Surface Mount | Surface Mount |
| Lead-Free (Pb-Free) | Yes (matte-tin, '-F' suffix) | — |
| RoHS 狀態 | [DATA_NEEDED: confirmed from manufacturer] | — |
| 記憶體類型 | Non-volatile (EEPROM configuration) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 128 |
| Usable Gates | — | 2,500 |
| Logic Array Blocks (LABs) | — | 8 (16 macro cells each) |
| User I/O Pins | — | 84 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency | — | 100 MHz |
| I/O Voltage Tolerance | — | 3.3 V or 5 V (MultiVolt interface) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE Std 1149.1), 4-pin |
| Lead-Free / RoHS Status | — | Lead-free (N suffix) |
| Architecture Generation | — | Second-generation MAX |