EPM7160ELC84-15 vs EPM7160ELC84-20 比較
詳細並排比較 EPM7160ELC84-15 由 Intel 與 EPM7160ELC84-20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7160ELC84-15 | EPM7160ELC84-20 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 7000 | MAX 7000 |
| Product Type | CPLD - Complex Programmable Logic Device | — |
| Architecture | EEPROM-based, second-generation MAX | Second-generation MAX |
| Usable Gates | 3,200 | 3,200 |
| Macrocells | 160 | 160 |
| Logic Array Blocks | 4 | 4 |
| Maximum I/O Pins | 36 | — |
| Pin-to-Pin Delay | 15 ns | — |
| Counter Frequency | 76.9 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Package Type | 84-pin PLCC (J-Lead) | — |
| 安裝類型 | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| 工作溫度 | 0 C to +70 C (commercial) | — |
| RoHS 狀態 | Contains lead / RoHS non-compliant (per Altera listing) | [DATA_NEEDED: RoHS compliance per specific part marking] |
| User I/O Pins | — | 64 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Programming Interface | — | IEEE 1149.1 JTAG (ISP) |
| In-System Programmable | — | Yes (5.0-V ISP) |
| 封裝 | — | PLCC-84 (windowed ceramic carrier not applicable - plastic) |
| Technology | — | CMOS EEPROM |
| Global Clock Inputs | — | 4 |
| Logic Element Type | — | EEPROM-based macrocell |