EPM7160SLC84-15 vs EPM7160SLC84-10 比較
詳細並排比較 EPM7160SLC84-15 由 Altera 與 EPM7160SLC84-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7160SLC84-15 | EPM7160SLC84-10 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 7000 | MAX 7000S |
| Macrocells | 160 | 160 |
| Usable Gates | 3,200 | 3,200 |
| Maximum Propagation Delay | 15 ns | — |
| Maximum User I/O Pins | 64 | 64 |
| Supply Voltage (VCCINT/VCIO) | 4.75 V to 5.25 V (5 V nominal) | — |
| I/O Logic Level | Configurable 3.3 V or 5 V | — |
| Technology | CMOS, EEPROM configuration | EEPROM-based CMOS |
| Package Type | PLCC-84 (PQCC84, JEDEC S-PQCC-J84) | — |
| Terminal Pitch | 1.270 mm | — |
| 安裝類型 | Surface Mount (PLCC socket or direct solder) | Surface Mount |
| 工作溫度 | 0 C to 70 C | 0C to +70C (Commercial) |
| Programming Interface | JTAG (IEEE 1149.1) in-system programmable | — |
| RoHS 狀態 | Not RoHS compliant (contains lead, SnPb finish typical) | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete / last-time-buy (per Altera/Intel PDN) | — |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG, 5.0 V) |
| 封裝 | — | 84-Pin PLCC (J-Lead) |
| JTAG Boundary Scan | — | Yes (IEEE Std. 1149.1 compliant) |