EPM7192EGI160-20 vs EPM7192EGM160-20 比較
詳細並排比較 EPM7192EGI160-20 由 Intel 與 EPM7192EGM160-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
EPM7192EGM160-20 Obsolete規格比較
| 參數 | EPM7192EGI160-20 | EPM7192EGM160-20 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 7000 | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EE CMOS CPLD (Electrically Erasable) |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 4 | — |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 4 | — |
| Pin-to-Pin Delay (tpd) | 20 ns | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Program Memory Type | EEPROM | — |
| In-System Programmability | Yes (JTAG IEEE Std. 1149.1) | — |
| 封裝 | 160-pin CPGA (Ceramic Pin Grid Array) | PGA-160 (160-pin Pin Grid Array) |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Programming Interface | JTAG (ByteBlaster / USB-Blaster compatible) | — |
| Logic Array Blocks (LABs) | — | 12 |
| Usable Gates | — | 600 to 5,000 |
| Maximum User I/O Pins | — | 120 |
| Speed Grade | — | -20 (20 ns pin-to-pin) |
| Pin-to-Pin Propagation Delay | — | 20 ns |
| Counter Frequency (max) | — | 175.4 MHz |
| I/O Standards | — | 3.3 V or 5 V configurable |
| Global Clock Inputs | — | 2 (GCLK1, GCLK2) |
| In-System Programming | — | Yes (JTAG IEEE 1149.1) |
| Program/Erase Endurance | — | 100 cycles (EEPROM) |
| 工作溫度 | — | -40C to +125C (industrial) |
| Technology Node | — | CMOS, second-generation MAX architecture |