EPM7192SQC160-10 vs EPM7192SQC160-15 比較
詳細並排比較 EPM7192SQC160-10 由 Altera 與 EPM7192SQC160-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7192SQC160-10 - 192-Macro MAX 7000S CPLD, 100MHz, PQFP-160 | Intel / Altera
EPM7192SQC160-10 Nrnd規格比較
| 參數 | EPM7192SQC160-10 | EPM7192SQC160-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 4 | — |
| User I/Os | 124 | — |
| Usable Gates | 3750 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | 76.9 MHz |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Program Memory Type | EEPROM | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| 封裝 | PQFP-160 (SQC) 28x28 mm | PQFP-160 |
| Pin/Package Type | Surface Mount, Gull-Wing | — |
| Operating Temperature (Commercial) | 0C to +70C | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | — |
| Lead Finish | [DATA_NEEDED: lead finish] | — |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Number of Macrocells | — | 192 |
| Number of Logic Array Blocks | — | 4 |
| Number of Usable Gates | — | 3750 |
| User I/O Pins | — | 124 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns |
| 供應電壓 | — | 5.0 V |
| Programmability | — | In-System (ISP) via JTAG IEEE Std 1149.1 |
| Configuration Memory | — | EEPROM, non-volatile |
| 安裝類型 | — | Surface Mount |
| 工作溫度範圍 | — | [DATA_NEEDED: operating temperature range] |
| Process Technology | — | CMOS, EEPROM-based |