EPM7256AETC144-10 vs EPM7256ATI144-10N 比較

詳細並排比較 EPM7256AETC144-10 由 Intel 與 EPM7256ATI144-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EPM7256ATI144-10N EPM7256ATI144-10N - 256-Macrocell MAX 7000A CPLD, 144-TQFP | Altera

EPM7256ATI144-10N - 256-Macrocell MAX 7000A CPLD, 144-TQFP | Altera

EPM7256ATI144-10N ⚠ 最後購買機會

規格比較

參數 EPM7256AETC144-10 EPM7256ATI144-10N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete 最後購買
Family MAX 7000A MAX 7000A
Series EPM7256AE —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 256 —
Usable Gates 5,000 5,000
Logic Array Blocks (LABs) 16 16
Maximum User I/Os 36 —
Dedicated Inputs 16 —
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Operating Frequency (fMAX) 95.2 MHz —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V (5.0 V tolerant inputs on A-series) —
封裝 144-pin TQFP (TQFP-144) TQFP-144
工作溫度 0C to +70C (commercial) -40C to +85C (industrial)
Programming Interface JTAG (IEEE 1149.1) + Fast Passive Serial —
Non-Volatile Memory EEPROM-based —
RoHS 狀態 [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS compliance per datasheet]
Macrocells — 256
User I/O Pins — [DATA_NEEDED: I/O count for 144-pin TQFP variant]
Pin-to-Pin Delay — 10 ns
Maximum Internal Frequency — 93.5 MHz
Supply Voltage VCCINT — 3.3 V
MultiVolt I/O Voltage VCCIO — 2.5 V or 3.3 V
Programming Method — IEEE Std. 1149.1 JTAG (ISP)
Non-volatile Configuration — Yes (EEPROM)

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