EPM7256AQC208-7 vs EPM7256SQC208-15N 比較
詳細並排比較 EPM7256AQC208-7 由 Altera 與 EPM7256SQC208-15N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7256AQC208-7 | EPM7256SQC208-15N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 7000A | — |
| Programmable Type | In System Programmable (ISP), EEPROM-based | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 164 | — |
| Pin-to-Pin Logic Delay (tPD) | 7 ns | — |
| Maximum Counter Frequency | 125 MHz | — |
| Internal Toggle Frequency | 227.3 MHz | — |
| Supply Voltage - Internal | 3.0 V to 3.6 V | — |
| I/O Voltage Compatibility | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) | — |
| 封裝 | 208-Pin PQFP (28 x 28 mm) | 208-pin PQFP |
| Supplier Device Package | 208-PQFP (28x28) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度範圍 | 0C to +70C (commercial) | — |
| JTAG Interface | IEEE 1149.1 (JTAG) boundary scan | IEEE 1149.1 boundary-scan |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Speed Grade | -7 | -15 |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Lead free / RoHS Compliant |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Series | — | MAX 7000S |
| User I/O Pins | — | 164 |
| Pin-to-Pin Delay | — | 15 ns (speed grade -15) |
| 供應電壓 | — | 5 V |
| In-System Programmability | — | Yes (ISP) |
| 工作溫度 | — | [DATA_NEEDED: operating temperature range] |
| Logic Array Blocks | — | 16 macrocells per LAB |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Product Category | — | CPLD - Complex Programmable Logic Devices |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |