EPM7256SRC208-15N vs EPM7256SQC208-7N 比較
詳細並排比較 EPM7256SRC208-15N 由 Altera 與 EPM7256SQC208-7N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7256SRC208-15N | EPM7256SQC208-7N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | MAX 7000S | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | 5,000 |
| User I/O Pins | 164 | 164 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Pin-to-Pin Delay (tPD) | 15 ns | 7.5 ns |
| Maximum Counter Frequency | 76.9 MHz | — |
| 供應電壓 | 5 V | — |
| Configuration Memory | EEPROM (non-volatile) | Non-volatile EEPROM (no external config needed) |
| 封裝 | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin PQFP (Plastic Quad Flat Pack) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0C to +70C (commercial) | Commercial (0C to +70C) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| I/O Standard | 5 V TTL/CMOS compatible | — |
| RoHS 狀態 | Compliant (N suffix) | Compliant (N suffix = lead-free) |
| Lead Free | Yes (N suffix) | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Number of Terminals | 208 | — |
| Family | — | MAX 7000S |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Speed Grade | — | -7 (7.5 ns pin-to-pin) |
| Maximum Frequency | — | 128.2 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS EEPROM |
| JTAG Interface | — | IEEE 1149.1 boundary-scan (ISP capable) |
| Minimum DC Input Voltage | — | -0.5 V |
| Input Undershoot Tolerance | — | -2.0 V for <100 mA, <20 ns |
| Open-Drain Output | — | Optional per I/O pin |