EPM9320LC84-20 vs EPM9400LC84-20 比較
詳細並排比較 EPM9320LC84-20 由 Altera 與 EPM9400LC84-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9320LC84-20 | EPM9400LC84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 400 |
| User I/Os | 60 | — |
| Logic Family | CMOS (EEPROM-based) | — |
| 封裝 | PLCC-84 (Plastic Leaded Chip Carrier) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Pins | 84 | — |
| Propagation Delay (tPD) | 16 ns | — |
| Internal Counter Frequency | 118 MHz | — |
| 供應電壓 | 5.0 V | — |
| 工作溫度 | 0 C to 70 C | Commercial (0C to +70C) - assumed from -20 speed grade |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Dedicated Inputs | 4 (global clock / clear / OE) | — |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | Multiple Array Matrix (MAX), 3rd generation, EEPROM-based |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Usable Gates | — | 8,000 (6,000 to 12,000 typical range) |
| Flip-Flops | — | 580 |
| Maximum User I/O | — | 55 |
| Pin-to-Pin Propagation Delay | — | 20 ns (speed grade -20) |
| Maximum Counter Frequency | — | 144 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| I/O Voltage (VCCIO) | — | 3.3 V or 5 V (configurable) |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Process Technology | — | CMOS EEPROM |
| 安裝類型 | — | Surface Mount (PLCC socket or SMT land pattern) |