EPM9480RC240-15 vs EPM9480RC240-20 比較
詳細並排比較 EPM9480RC240-15 由 Altera 與 EPM9480RC240-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9480RC240-15 | EPM9480RC240-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Programmable Type | In System Programmable (ISP) | — |
| Device Family | MAX 9000 | — |
| Macro Cells | 480 | — |
| Usable Gates | 12,000 | 10,000 |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Internal Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Configuration Technology | EEPROM-based (non-volatile) | — |
| JTAG Interface | IEEE Std. 1149.1 | — |
| 封裝 | 240-pin RQFP (32x32 mm) | 240-RQFP (32x32 mm, FQFP, Gull Wing) |
| Supplier Device Package | 240-RQFP (32x32) | — |
| 安裝類型 | Surface Mount | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | — |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | — |
| RoHS 狀態 | RoHS non-compliant | [DATA_NEEDED: RoHS status] |
| Lead Free Status | [DATA_NEEDED: lead free status] | — |
| Logic Architecture | Multiple Array MatriX (MAX) third-generation | — |
| Supply Voltage (5.0 V nominal) | 5.0 V | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 480 |
| Logic Elements | — | 30 |
| User I/O Pins | — | 175 |
| Number of Terminals | — | 240 |
| Maximum Propagation Delay (tpd) | — | 20 ns |
| Maximum Internal Frequency (fMAX, related -C variant) | — | 100 MHz |
| Programmable Flip-Flops (family) | — | 676 |
| I/O Signaling Levels | — | 3.3 V or 5 V (configurable) |
| Process Technology | — | CMOS EEPROM |
| Programming Interface | — | In-System Programmable (ISP) via IEEE 1149.1 JTAG |
| Operating Temperature Grade | — | Commercial |
| Terminal Form | — | Gull Wing |