EPM9560GC280-15N vs EPM9560GC280-20N 比較
詳細並排比較 EPM9560GC280-15N 由 Intel 與 EPM9560GC280-20N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560GC280-15N | EPM9560GC280-20N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Device Family | MAX 9000 | — |
| Product Type | EE PLD / CPLD | — |
| Macrocell Count | 560 | — |
| Usable Gates | 12,000 (typical) | 6,000 to 12,000 |
| Propagation Delay (tPD) | 16.6 ns | — |
| 最大時脈頻率 | 117.6 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Maximum Supply Voltage | 5.25 V | — |
| Logic Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (5.0-V ISP via JTAG) | Yes (5.0-V ISP via IEEE 1149.1 JTAG) |
| Boundary-Scan (JTAG) | IEEE Std. 1149.1 compliant | — |
| 封裝 | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | 280-pin CPGA (Ceramic Pin Grid Array) |
| Package Code | PGA / CPGA280 | — |
| Terminal Form | PIN/PEG | — |
| Operating Temperature Grade | Commercial | — |
| Architecture | Multiple Array MatriX (MAX) 3rd generation | Multiple Array MatriX (MAX), 3rd generation |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Technology | — | CMOS EEPROM-based |
| Macrocells | — | 560 |
| User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Maximum Counter Frequency | — | 144 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| I/O Voltage | — | 3.3 V or 5 V (configurable) |
| Configuration Memory | — | EEPROM (non-volatile, instant-on) |
| PCI Compliance | — | Yes |
| 工作溫度 | — | [DATA_NEEDED: industrial/commercial grade] |
| RoHS 狀態 | — | [DATA_NEEDED] |