EPM9560GC280-15N vs EPM9560GC280-20N Comparison
Detailed side-by-side comparison of EPM9560GC280-15N by Intel and EPM9560GC280-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560GC280-15N | EPM9560GC280-20N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $125.00 | $285.00 |
| Device Family | MAX 9000 | β |
| Product Type | EE PLD / CPLD | β |
| Macrocell Count | 560 | β |
| Usable Gates | 12,000 (typical) | 6,000 to 12,000 |
| Propagation Delay (tPD) | 16.6 ns | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | β |
| Maximum Supply Voltage | 5.25 V | β |
| Logic Technology | CMOS EEPROM | β |
| In-System Programmability | Yes (5.0-V ISP via JTAG) | Yes (5.0-V ISP via IEEE 1149.1 JTAG) |
| Boundary-Scan (JTAG) | IEEE Std. 1149.1 compliant | β |
| Package | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | 280-pin CPGA (Ceramic Pin Grid Array) |
| Package Code | PGA / CPGA280 | β |
| Terminal Form | PIN/PEG | β |
| Operating Temperature Grade | Commercial | β |
| Architecture | Multiple Array MatriX (MAX) 3rd generation | Multiple Array MatriX (MAX), 3rd generation |
| Family | β | MAX 9000 |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Technology | β | CMOS EEPROM-based |
| Macrocells | β | 560 |
| User I/O Pins | β | 212 |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Maximum Counter Frequency | β | 144 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| I/O Voltage | β | 3.3 V or 5 V (configurable) |
| Configuration Memory | β | EEPROM (non-volatile, instant-on) |
| PCI Compliance | β | Yes |
| Operating Temperature | β | [DATA_NEEDED: industrial/commercial grade] |
| RoHS Status | β | [DATA_NEEDED] |