EPM9560GI280-20 vs EPM9560GI280-15 比較
詳細並排比較 EPM9560GI280-20 由 Intel 與 EPM9560GI280-15 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560GI280-20 | EPM9560GI280-15 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Device Family | MAX 9000 | MAX 9000 |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | CMOS EEPROM, third-generation Multiple Array MatriX (MAX) |
| Technology Node | 5.0 V CMOS EEPROM | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 28 (16 macrocells each) | — |
| Usable Gates | 12,000 | — |
| Maximum User I/O Pins | 216 | — |
| Flip-Flops | 772 | 772 |
| Pin-to-Pin Delay (Speed Grade) | 20 ns | — |
| Supply Voltage (VCC) | 5.0 V | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | 5.0-V ISP via JTAG |
| Programming Technology | EEPROM (non-volatile) | — |
| 封裝 | 280-pin PGA (PIN/PEG, square) | 280-pin PGA (ceramic, metal-sealed cofired) |
| Terminal Form | PIN/PEG (through-hole PGA) | — |
| Package Code | PGA | — |
| Temperature Grade | Industrial | — |
| I/O Pin DC Input Range | -0.5 V to VCC + 0.5 V | — |
| Dedicated-Input Pin DC Input Range | -0.3 V to VCC + 0.3 V | — |
| I/O Transient Envelope (no-load, <20 ns) | -2.0 V undershoot to 7.0 V overshoot | — |
| VCC Ramp Requirement | Monotonic rise | — |
| Development Tool | Altera MAX+PLUS II | — |
| Supported HDLs | VHDL, Verilog HDL, AHDL | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status for GI PGA package] | [DATA_NEEDED: RoHS status] |
| User I/Os | — | 216 |
| Dedicated Inputs | — | 12 |
| Logic Elements / Gates | — | 12,000 usable gates |
| Internal Frequency (fMAX) | — | 145 MHz |
| Propagation Delay (tPD) | — | 11.4 ns |
| Clock-to-Output (tCO) | — | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 4.5 V to 5.5 V (3.3 V or 5 V I/O) |
| 工作溫度 | — | -40 °C to 85 °C (industrial) |
| Process Technology | — | CMOS EEPROM |
| 濕度敏感等級 (MSL) | — | MSL-3 (168 hours) |