EPM9560RC-15 vs EPM9560RC-10 比較
詳細並排比較 EPM9560RC-15 由 Altera 與 EPM9560RC-10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel
EPM9560RC-15 ⚠ 最後購買機會規格比較
| 參數 | EPM9560RC-15 | EPM9560RC-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| Logic Array Blocks (LABs) | 16 (40 macrocells each) | 16 |
| Maximum User I/O Pins | 191 | 212 |
| Pin-to-Pin Delay (tPD1) | 15 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| 工作溫度 | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| 封裝 | 240-pin RQFP (32x32 mm) | 240-pin PGA (RC suffix) |
| 安裝類型 | Surface Mount | Through-Hole / Socketed |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array Matrix (MAX) - third generation |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | unknown |
| In-System Programmability | Yes (5.0 V ISP via JTAG) | IEEE 1149.1 JTAG |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |