EPM9560RC208-10N vs EPM9560RC208-12 比較
詳細並排比較 EPM9560RC208-10N 由 Intel 與 EPM9560RC208-12 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC208-10N | EPM9560RC208-12 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device | EPM9560 | — |
| Macro Cells | 560 | — |
| Usable Gates | 12,000 | 12000 |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 153 | — |
| Pin-to-Pin Delay (tPD1) | 10 ns | — |
| Supply Voltage (VCCINT) | 5.0 V | 5 V |
| I/O Bank Voltage (VCCIO) | 5.0 V | — |
| 封裝 | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (S-PQFP-G208) |
| 安裝類型 | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| 工作溫度 | [DATA_NEEDED: operating temperature grade] | 0C to +70C (commercial) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device Type | — | EEPROM-based CPLD |
| Macrocells | — | 560 |
| Flip-Flops | — | 772 |
| User I/O Lines | — | 153 |
| Propagation Delay (tPD) | — | 12 ns |
| 最大時脈頻率 | — | 125 MHz |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Terminal Pitch | — | 0.50 mm |
| Configuration Memory | — | EEPROM (non-volatile) |
| Logic Array Blocks | — | 20 |
| Speed Grade | — | -12 (12 ns) |